Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming

Abstract

The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18 /spl mu/m technology and the resulting active layout area is 0.14 mm/sup 2/, while its total power consumption is below 40 mW.