Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213035
J. Northern, M. Shanblatt
Power consumption and portability issues are increasingly significant in system-on-a-chip applications. As a result, it is important that power and performance tradeoffs are made more visible to chip architects and circuit designers. Next generation tools are being developed to achieve high accuracy by estimating power consumption earlier in the design process. These tools also allow the designer to explore different configurations in a given design space. As the design space continues to expand, more efficient search methods are needed. This paper presents a framework for an evolutionary approach to configuring an ideal embedded processor based on power consumption.
{"title":"An evolutionary approach to configuring an embedded system based on power consumption","authors":"J. Northern, M. Shanblatt","doi":"10.1109/IWSOC.2003.1213035","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213035","url":null,"abstract":"Power consumption and portability issues are increasingly significant in system-on-a-chip applications. As a result, it is important that power and performance tradeoffs are made more visible to chip architects and circuit designers. Next generation tools are being developed to achieve high accuracy by estimating power consumption earlier in the design process. These tools also allow the designer to explore different configurations in a given design space. As the design space continues to expand, more efficient search methods are needed. This paper presents a framework for an evolutionary approach to configuring an ideal embedded processor based on power consumption.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125397148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213056
M. Chowdhury, Y. Ismail
Noise has become an important metric of deep submicron digital integrated circuit performance, and is becoming even more prominent due to the increasing usage of noise sensitive dynamic circuits for speed and area requirements. This paper presents closed form analytical solutions for noise as well as noise tolerance metrics for dynamic circuits to analyze the effects of coupling, which is considered as the dominant source of noise. These solutions are within 5% of dynamic simulations. It is shown that not all the scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency help improve certain aspects of the noise immunity of dynamic circuit. Most of the work treated noise immunity and the noise content separately. This paper introduces a positive analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.
{"title":"Analysis of coupling noise in dynamic circuit","authors":"M. Chowdhury, Y. Ismail","doi":"10.1109/IWSOC.2003.1213056","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213056","url":null,"abstract":"Noise has become an important metric of deep submicron digital integrated circuit performance, and is becoming even more prominent due to the increasing usage of noise sensitive dynamic circuits for speed and area requirements. This paper presents closed form analytical solutions for noise as well as noise tolerance metrics for dynamic circuits to analyze the effects of coupling, which is considered as the dominant source of noise. These solutions are within 5% of dynamic simulations. It is shown that not all the scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency help improve certain aspects of the noise immunity of dynamic circuit. Most of the work treated noise immunity and the noise content separately. This paper introduces a positive analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129067412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1212996
Sérgio G. Araújo, A. C. M. Filho, A. Pedroza
High-level design entry tools offer a nice framework to deal with today's complex systems while shortening the design cycle. Nevertheless, such tools provide poor quality results both in area usage and timing performance issues. This paper presents a methodology to design optimized datapaths based on evolutionary techniques and HLS tools. VHDL descriptions of the system are automatically generated by Genetic Programming. To improve the design of the structural quality of such descriptions, a two-stage multi-objective optimization algorithm is used to ensure both desired functionality and area constraints.
{"title":"Optimized datapath design by evolutionary computation","authors":"Sérgio G. Araújo, A. C. M. Filho, A. Pedroza","doi":"10.1109/IWSOC.2003.1212996","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1212996","url":null,"abstract":"High-level design entry tools offer a nice framework to deal with today's complex systems while shortening the design cycle. Nevertheless, such tools provide poor quality results both in area usage and timing performance issues. This paper presents a methodology to design optimized datapaths based on evolutionary techniques and HLS tools. VHDL descriptions of the system are automatically generated by Genetic Programming. To improve the design of the structural quality of such descriptions, a two-stage multi-objective optimization algorithm is used to ensure both desired functionality and area constraints.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134444460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1212998
Kuo-Hsing Cheng, Wei-chun Chang, C. Tu
In this paper, a new handshake methodology to enhance the performance of the asynchronous systems is proposed. The proposed handshake methodology has more flexibility to design an asymmetric asynchronous system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. In others the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. Finally, an asynchronous array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35 /spl mu/m CMOS technology, the simulation result of the maximum throughput is about 2.5 ns.
{"title":"A robust handshake for asynchronous system","authors":"Kuo-Hsing Cheng, Wei-chun Chang, C. Tu","doi":"10.1109/IWSOC.2003.1212998","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1212998","url":null,"abstract":"In this paper, a new handshake methodology to enhance the performance of the asynchronous systems is proposed. The proposed handshake methodology has more flexibility to design an asymmetric asynchronous system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. In others the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. Finally, an asynchronous array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35 /spl mu/m CMOS technology, the simulation result of the maximum throughput is about 2.5 ns.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"2 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132870585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213066
E. Dumitrescu, D. Borrione
The successful application of model-checking to industrial designs requires methods for reducing the complexity of the model. This paper presents an original strategy, for a well identified class of circuit behaviors; by running an appropriate symbolic simulation pattern before the actual proof of a temporal formula, an important FSM model simplification can be obtained. The actual model reduction step is formalized and illustrated. This method has been implemented within the CMU version of the SMV model checking tool and validated on a large industrial design.
{"title":"Symbolic simulation as a simplifying strategy for SoC verification","authors":"E. Dumitrescu, D. Borrione","doi":"10.1109/IWSOC.2003.1213066","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213066","url":null,"abstract":"The successful application of model-checking to industrial designs requires methods for reducing the complexity of the model. This paper presents an original strategy, for a well identified class of circuit behaviors; by running an appropriate symbolic simulation pattern before the actual proof of a temporal formula, an important FSM model simplification can be obtained. The actual model reduction step is formalized and illustrated. This method has been implemented within the CMU version of the SMV model checking tool and validated on a large industrial design.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114687775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213051
C.-S. Seo, A. Chatterjee
An efficient co-optimization algorithm of placement and routing for high-performance multichip module (MCM) systems utilizing free-space optical interconnect technology is introduced. A computer-aided design (CAD) tool is developed for optimizing placement of modules and routing of electro-optic interconnects simultaneously without exceeding the routing capacity of the optical interconnect. About 48% saving in total routing cost is achieved through the use of 600 optical interconnects with 100 modules. It translates to doubling of the MCM performance.
{"title":"Free-space optical interconnect for high-performance MCM systems","authors":"C.-S. Seo, A. Chatterjee","doi":"10.1109/IWSOC.2003.1213051","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213051","url":null,"abstract":"An efficient co-optimization algorithm of placement and routing for high-performance multichip module (MCM) systems utilizing free-space optical interconnect technology is introduced. A computer-aided design (CAD) tool is developed for optimizing placement of modules and routing of electro-optic interconnects simultaneously without exceeding the routing capacity of the optical interconnect. About 48% saving in total routing cost is achieved through the use of 600 optical interconnects with 100 modules. It translates to doubling of the MCM performance.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128177246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213034
J. L. Silva, R. Costa, G. Jorge
This paper describes the purpose of development for RtrASSoc, an Adaptable, Superscalar and Reconfigurable System on Chip. The RtrASSoc will be used in Embedded Systems that need capacity, performance, and low cost, based on Programmable System-on-Chip (PSOC), where part of the system will be a embedded superscalar processor (ESP), another part will be a Embedded Operating System (EOS), and finally a reconfigurable part where a reconfigurable routines (RR) can be reconfigured, extracted from the application program. A C-compiler extracts the reconfigurable routines from the application program and fix the parameters for reconfiguration that will be used during the execution of the application. The system will be tested in recognition pattern applications in a FPGA Virtex from Xilinx.
{"title":"RtrASSoc: an adaptable superscalar reconfigurable system-on-chip. The simulator","authors":"J. L. Silva, R. Costa, G. Jorge","doi":"10.1109/IWSOC.2003.1213034","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213034","url":null,"abstract":"This paper describes the purpose of development for RtrASSoc, an Adaptable, Superscalar and Reconfigurable System on Chip. The RtrASSoc will be used in Embedded Systems that need capacity, performance, and low cost, based on Programmable System-on-Chip (PSOC), where part of the system will be a embedded superscalar processor (ESP), another part will be a Embedded Operating System (EOS), and finally a reconfigurable part where a reconfigurable routines (RR) can be reconfigured, extracted from the application program. A C-compiler extracts the reconfigurable routines from the application program and fix the parameters for reconfiguration that will be used during the execution of the application. The system will be tested in recognition pattern applications in a FPGA Virtex from Xilinx.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121109668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213064
J. Rau, Yi-Yuan Chang, Chia-Hung Lin
In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.
{"title":"An efficient mechanism for debugging RTL description","authors":"J. Rau, Yi-Yuan Chang, Chia-Hung Lin","doi":"10.1109/IWSOC.2003.1213064","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213064","url":null,"abstract":"In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123804678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213050
Tao Lin, Zhou Zhengou
A high-speed data acquisition based on FPGA and implemented in VHDL is presented in this paper. According to the requirement of a new radar system, several new technologies are adopted in the design and implementation such as time compression storage and memory rewriting. As a result, the system performs well with low dissipation of power, simple circuit layout and high efficient utilization of memory. The acquisition system comprises four parts: ADC circuit, data package and interface, sampling data memory and data flag memory. To implement large circuit, FPGA is adopted in this data acquisition system with reconfigurable ability and constant delay feature according to Z.G. Vranesic (1999).
{"title":"The implementation of 100MHz data acquisition based on FPGA","authors":"Tao Lin, Zhou Zhengou","doi":"10.1109/IWSOC.2003.1213050","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213050","url":null,"abstract":"A high-speed data acquisition based on FPGA and implemented in VHDL is presented in this paper. According to the requirement of a new radar system, several new technologies are adopted in the design and implementation such as time compression storage and memory rewriting. As a result, the system performs well with low dissipation of power, simple circuit layout and high efficient utilization of memory. The acquisition system comprises four parts: ADC circuit, data package and interface, sampling data memory and data flag memory. To implement large circuit, FPGA is adopted in this data acquisition system with reconfigurable ability and constant delay feature according to Z.G. Vranesic (1999).","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131197405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213003
K. Vivekanandarajah, T. Srikanthan, S. Bhattacharyya, Prasanna Venkatesh Kannan
A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 256 Bytes. Prediction algorithms popularly based upon the Next Fetch Prediction Table (NFPT) help making the choice between the filter cache and the main cache. In this paper we introduce a new prediction mechanism for predicting filter cache access, which relies on the hit or miss pattern of the instruction access stream over the past filter cache lines accesses. While NFPT makes predominantly incorrect hit-predictions, the proposed Pattern Table based approach reduces this. Predominantly correct prediction achieves efficient cache access, and eliminates cache-miss penalties. Our extensive simulations across a wide range of benchmark applications illustrate that the new prediction scheme is efficient as it results in improved prediction accuracy. Moreover, it reduces energy consumption of the filter cache by as much as 25% compared to NFPT based approaches. Further, the technique implemented is elegant in the form of hardware implementation as it consists only of a shift register and a Look up Table (LUT) and is hence area and energy efficient in contrast to the published prediction techniques.
{"title":"Incorporating pattern prediction technique for energy efficient filter cache design","authors":"K. Vivekanandarajah, T. Srikanthan, S. Bhattacharyya, Prasanna Venkatesh Kannan","doi":"10.1109/IWSOC.2003.1213003","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213003","url":null,"abstract":"A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 256 Bytes. Prediction algorithms popularly based upon the Next Fetch Prediction Table (NFPT) help making the choice between the filter cache and the main cache. In this paper we introduce a new prediction mechanism for predicting filter cache access, which relies on the hit or miss pattern of the instruction access stream over the past filter cache lines accesses. While NFPT makes predominantly incorrect hit-predictions, the proposed Pattern Table based approach reduces this. Predominantly correct prediction achieves efficient cache access, and eliminates cache-miss penalties. Our extensive simulations across a wide range of benchmark applications illustrate that the new prediction scheme is efficient as it results in improved prediction accuracy. Moreover, it reduces energy consumption of the filter cache by as much as 25% compared to NFPT based approaches. Further, the technique implemented is elegant in the form of hardware implementation as it consists only of a shift register and a Look up Table (LUT) and is hence area and energy efficient in contrast to the published prediction techniques.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114540416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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