Improved Route Selection Approaches using Q-learning framework for 2D NoCs

Niyati Gupta, Manoj Kumar, Ashish Sharma, M. Gaur, V. Laxmi, M. Daneshtalab, M. Ebrahimi
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引用次数: 10

Abstract

With the emergence of large multi-core architectures, a volume of research has been focused on distributing traffic evenly over the whole network. However, increase in traffic density may lead to congestion and subsequently degrade the performance by increased latency in the network. In this paper, we propose two novel route selection strategies for on-chip networks which are based on the Q-learning framework. The proposed strategies use variable learning rate to dynamically capture the current congestion status of the network using an additional parameter and improves the learning process to select a less congested output channel. Both the proposed selection strategies are found to adapt significantly faster to the changes in traffic load and traffic patterns by avoiding congested areas. The results demonstrate that proposed strategies achieve significant performance improvement over conventional Q-routing and its variants with slight area-overhead.
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基于q -学习框架的2D noc改进路径选择方法
随着大型多核架构的出现,如何在全网内均匀分配流量成为人们关注的焦点。但是,流量密度的增加可能导致拥塞,并通过增加网络中的延迟来降低性能。本文提出了两种基于q -学习框架的片上网络路由选择策略。该策略使用可变学习率来动态捕获网络的当前拥塞状态,并使用附加参数改进学习过程以选择拥塞较少的输出通道。结果表明,这两种选择策略都能避开拥堵区域,从而更快地适应交通负荷和交通模式的变化。结果表明,与传统的q路由及其变体相比,所提出的策略在较小的面积开销下实现了显着的性能改进。
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Improved Route Selection Approaches using Q-learning framework for 2D NoCs Proceedings of the 3rd International Workshop on Many-core Embedded Systems Hardware Scheduler Performance on the Plural Many-Core Architecture Parallel Programming Model for the Epiphany Many-Core Coprocessor Using Threaded MPI A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias
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