Matthiew Franks, N. Massari, L. Parmesan, G. Casse
{"title":"A novel fully digital particle detector with high spatial resolution","authors":"Matthiew Franks, N. Massari, L. Parmesan, G. Casse","doi":"10.1109/prime55000.2022.9816828","DOIUrl":null,"url":null,"abstract":"In the presented paper we describe an innovative pixel topology designed for particle tracking. The proposed approach is based on a fully digital concept. When ionising particles traverse detector material, charges collected by the pixel are converted to a single bit to obtain a binary image. This digital approach allows a simplified pixel schematic to be used, reducing the pixel size to 2.5 μm × 2.5 μm and optimises the power consumption and the speed of the readout. An array of 256×256 pixels have been fabricated in a 65 nm standard CMOS technology as a proof of concept. Preliminary results on pixel performance are reported, demonstrating the potential of the approach.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/prime55000.2022.9816828","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In the presented paper we describe an innovative pixel topology designed for particle tracking. The proposed approach is based on a fully digital concept. When ionising particles traverse detector material, charges collected by the pixel are converted to a single bit to obtain a binary image. This digital approach allows a simplified pixel schematic to be used, reducing the pixel size to 2.5 μm × 2.5 μm and optimises the power consumption and the speed of the readout. An array of 256×256 pixels have been fabricated in a 65 nm standard CMOS technology as a proof of concept. Preliminary results on pixel performance are reported, demonstrating the potential of the approach.