Density enhancement of a neural network using FPGAs and run-time reconfiguration

Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines Pub Date : 1994-04-10 DOI:10.1109/FPGA.1994.315611

James G. Eldredge, B. L. Hutchings

{"title":"Density enhancement of a neural network using FPGAs and run-time reconfiguration","authors":"James G. Eldredge, B. L. Hutchings","doi":"10.1109/FPGA.1994.315611","DOIUrl":null,"url":null,"abstract":"Run-time reconfiguration is a way of more fully exploiting the flexbility of reconfigurable FPGAs. The run-time reconfiguration artificial neural network (RRANN) uses ran-time reconfiguration to increase the hardware density of FPGAs. The RRANN architecture also allows large amounts of parallelism to be used and is very scalable. RRANN divides the back-propagation algorithm into three sequential executed stages and configures the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single Xilinx XC3090 can implement by 500%. Performance is effected by reconfiguration overhead, but this overhead becomes insignificant in large networks. This overhead is made even more insignificant with improved configuration methods. Run-time reconfiguration is a flexible realization of the time/space trade-off. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured.<<ETX>>","PeriodicalId":138179,"journal":{"name":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"117","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPGA.1994.315611","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 117

Abstract

Run-time reconfiguration is a way of more fully exploiting the flexbility of reconfigurable FPGAs. The run-time reconfiguration artificial neural network (RRANN) uses ran-time reconfiguration to increase the hardware density of FPGAs. The RRANN architecture also allows large amounts of parallelism to be used and is very scalable. RRANN divides the back-propagation algorithm into three sequential executed stages and configures the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single Xilinx XC3090 can implement by 500%. Performance is effected by reconfiguration overhead, but this overhead becomes insignificant in large networks. This overhead is made even more insignificant with improved configuration methods. Run-time reconfiguration is a flexible realization of the time/space trade-off. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured.<>

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基于fpga和运行时重构的神经网络密度增强

运行时重构是一种更充分利用可重构fpga灵活性的方法。运行时重构人工神经网络(RRANN)利用运行时重构来提高fpga的硬件密度。RRANN架构还允许使用大量的并行性，并且具有很强的可扩展性。RRANN将反向传播算法划分为三个顺序执行的阶段，并配置fpga一次只执行一个阶段。为了改变阶段，fpga被重新配置为正常执行的一部分。以这种方式使用可重构性使单个Xilinx XC3090可以实现的硬件神经元数量增加了500%。性能会受到重新配置开销的影响，但这种开销在大型网络中变得微不足道。通过改进配置方法，这种开销变得更加微不足道。运行时重新配置是时间/空间权衡的灵活实现。RRANN架构是使用商用硬件设计和构建的，并对其性能进行了测量。

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Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines

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