Recognizing Geometric Path from Polygon-Based Integrated Circuit Layout

Abstract

As the continual decrease of the feature size, the parasitic inductance and capacitance effect play important role in IC design and verification. Previous works on layout extraction mainly concentrated on how to find out the type of devices and connections between them, few works has addressed the information of centerlines and widths of IC interconnects in a polygon-based VLSI layout, which are required in inductance calculation and other applications. In this paper, an efficient scheme for the centerline-based path recognition from an IC mask layout is presented. Unlike the division-based methods, a tree-traverse-based approach is proposed. This new scheme can be realized as a reverse procedure of the layout generation from wire routing trees. Moreover, this scheme can handle complex all-angle wires. Experimental results show that this scheme has nearly linear computational complexity yet generates precise results.