Stress reduction methods within the Far Back End of Line (FBEOL) for fine pitch and 2.5D/3D packaging configurations

Abstract

Fine pitch interconnects combined with 2.5D/3D packaging technology offers enormous potential towards decreasing signal latency and by making it possible to package increased electrical functionality within a given area. However, fine pitch interconnects present their own set of challenges not seen in packages with coarse pitch interconnects. Increased stresses within the Far Back End of Line (FBEOL) and Back End of Line (BEOL) layers within the chip are the primary concerns. Several 2D and 2.5D test vehicles with fine pitch and coarse pitch interconnects were built and tested for mechanical integrity by subjecting them to accelerated thermal cycling between -55°C and 125°C. Finite-element based mechanical modeling was done to determine the stress level within the FBEOL layers of these test vehicles. For all the tested assemblies, experimental data and modeling results showed a strong correlation between reduced pitch and increased level of stresses and increased incidence of failures within the FBEOL region. These failures were observed exclusively at the passivation layer and aluminum pad inter face. Experimental data in conjunction with mechanical modeling was used to determine a safe level of stress at the aluminum interface. Global and local design changes were explored to determine their effect on the stresses at this interface. Several guidelines have been provided to reduce these stresses for a 2.5D/3D package assembly with fine pitch interconnects. Finally, an optimized configuration has been proposed that is expected to be robust with very low chance of failure within the FBEOL region.