{"title":"A High Linearity and Low Load Regulation LDO with SATEC and TIR Compensation","authors":"Siwan Dong, Sen Bu","doi":"10.1109/iccss55260.2022.9802344","DOIUrl":null,"url":null,"abstract":"A high linearity and low load regulation LDO with SATEC and TIR compensation is proposed in this paper. The sub-amplifier transconductance-enhancement compensation (SATEC) and transistor impedance regulation (TIR) structures are proposed to improve the linearity and load regulation. The LDO loop gain and phase margin (PM) are enhanced mainly by compensating and increasing the transconductance. The verification of design is completed under a standard 0.1Sμm CMOS process. The simulation results show that within the scope of output voltage ranges from 1. 0V to 1. 6V and input ranges from 1. 2V to 1.SV. The proposed LDO structure has linear regulation rate of 0.301mV/V and load regulation rate of 0. 000023mV/A, with withstands load current transients up to 120mA and remain over 60dB PSR at 10kHz.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iccss55260.2022.9802344","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A high linearity and low load regulation LDO with SATEC and TIR compensation is proposed in this paper. The sub-amplifier transconductance-enhancement compensation (SATEC) and transistor impedance regulation (TIR) structures are proposed to improve the linearity and load regulation. The LDO loop gain and phase margin (PM) are enhanced mainly by compensating and increasing the transconductance. The verification of design is completed under a standard 0.1Sμm CMOS process. The simulation results show that within the scope of output voltage ranges from 1. 0V to 1. 6V and input ranges from 1. 2V to 1.SV. The proposed LDO structure has linear regulation rate of 0.301mV/V and load regulation rate of 0. 000023mV/A, with withstands load current transients up to 120mA and remain over 60dB PSR at 10kHz.
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