Integrated 85V rated complimentary LDMOS devices utilizing patterned field plate structures for best-in-class performance in network communication applications

Abstract

This paper presents complimentary 85V-rated LDMOS devices integrated in a 180nm power management technology platform. The devices are fabricated using a design technique which utilizes tapered dielectric regions in combination with patterned floating field plated structures. The performance of the new structures are compared to conventional LDMOS structures and it shown that the floating field plated structures have superior BV_ds-R_{on, sp}, HCI reliability, and forward safe operating area figures-of-merit. These devices exhibit best-in-class BV_ds-R_{on, sp} figure-of-merit (NLDMOS : BV_ds=130V/R_{on, sp}=195mΩ.mm² and PLDMOS : BV_ds=140V/R_{on, sp}=530mΩ.mm²) and hot carrier reliability in excess of 10 years analog lifetime for rated V_DS = 85V and full range of V_GS. These devices enable cost effective integration of PoE systems with multiple interface channels and auxiliary switching regulators.