Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694415
Wentong Zhang, M. Qiao, Lijuan Wu, Ke Ye, Zhuo Wang, Zhigang Wang, X. Luo, Sen Zhang, Wei Su, Bo Zhang, Zhaoji Li
An ultra-low specific on-resistance (Ron, sp) high voltage trench SOI LDMOS based on the enhanced bulk field (ENBULF) concept is proposed. The key feature of this new device is heavily doped N/P pillars parallel to the trench oxide layer. The bulk electric field of the trench LDMOS is enhanced both in the dielectric and the silicon layer by using the N/P pillars. Firstly, the highly doped N/P pillars introduce two new electric field peaks in the bulk of the drift region, which enhances the bulk electric fields both under the drain and source. Secondly, the additional electric field of the trench oxide layer is produced by N/P pillars, leading to a shrink of the drift area. Thirdly, the enhanced dielectric layer field (ENDIF) effect of the BOX layer occurs self-adaptively with different thicknesses of the BOX layer. Combining the trench and SJ technologies, the cell pitch is reduced and the optimized doping concentration of the drift region is increased. The Ron,sp is therefore reduced efficiently. The 2-D analytical model of the ENBULF LDMOS is developed to guide the design of the novel device. Based on the model and the simulation, the ENBULF LDMOS exhibits a offstate BV of 684 V and a Ron, sp of 48.5 mΩ·cm2. The new device breaks through the silicon limit in a wide applied voltage levels.
{"title":"Ultra-low specific on-resistance SOI high voltage trench LDMOS with dielectric field enhancement based on ENBULF concept","authors":"Wentong Zhang, M. Qiao, Lijuan Wu, Ke Ye, Zhuo Wang, Zhigang Wang, X. Luo, Sen Zhang, Wei Su, Bo Zhang, Zhaoji Li","doi":"10.1109/ISPSD.2013.6694415","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694415","url":null,"abstract":"An ultra-low specific on-resistance (Ron, sp) high voltage trench SOI LDMOS based on the enhanced bulk field (ENBULF) concept is proposed. The key feature of this new device is heavily doped N/P pillars parallel to the trench oxide layer. The bulk electric field of the trench LDMOS is enhanced both in the dielectric and the silicon layer by using the N/P pillars. Firstly, the highly doped N/P pillars introduce two new electric field peaks in the bulk of the drift region, which enhances the bulk electric fields both under the drain and source. Secondly, the additional electric field of the trench oxide layer is produced by N/P pillars, leading to a shrink of the drift area. Thirdly, the enhanced dielectric layer field (ENDIF) effect of the BOX layer occurs self-adaptively with different thicknesses of the BOX layer. Combining the trench and SJ technologies, the cell pitch is reduced and the optimized doping concentration of the drift region is increased. The Ron,sp is therefore reduced efficiently. The 2-D analytical model of the ENBULF LDMOS is developed to guide the design of the novel device. Based on the model and the simulation, the ENBULF LDMOS exhibits a offstate BV of 684 V and a Ron, sp of 48.5 mΩ·cm2. The new device breaks through the silicon limit in a wide applied voltage levels.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121135516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694436
Liheng Zhu, Xingbi Chen
A novel reverse-conducting insulated gate bipolar transistor (RC-IGBT) with anti-parallel Shockley diode is proposed. By introducing an additional isolated p-n junction at the anode, the effect of anode-short is eliminated, and accordingly, the snapback problem is solved in the novel RC-IGBT. The snapback-free characteristics can be realized in a single cell with a width of less than 10 μm. Besides, the conduction voltages are significantly reduced and the distributions of minority carrier and of current are more uniform than the conventional RC-IGBT, in both the forward and the reverse conduction states. The tradeoff between Eoff and Von in the forward operation case and the tradeoff between Qrr and Von in the reverse operation case are both optimized in this paper.
{"title":"A novel snapback-free reverse conducting IGBT with anti-parallel Shockley diode","authors":"Liheng Zhu, Xingbi Chen","doi":"10.1109/ISPSD.2013.6694436","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694436","url":null,"abstract":"A novel reverse-conducting insulated gate bipolar transistor (RC-IGBT) with anti-parallel Shockley diode is proposed. By introducing an additional isolated p-n junction at the anode, the effect of anode-short is eliminated, and accordingly, the snapback problem is solved in the novel RC-IGBT. The snapback-free characteristics can be realized in a single cell with a width of less than 10 μm. Besides, the conduction voltages are significantly reduced and the distributions of minority carrier and of current are more uniform than the conventional RC-IGBT, in both the forward and the reverse conduction states. The tradeoff between Eoff and Von in the forward operation case and the tradeoff between Qrr and Von in the reverse operation case are both optimized in this paper.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127156642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694474
S. Sundaresan, M. Marripelly, Svetlana Arshavsky, R. Singh
This paper reports on ultra-high voltage, >15 kV SiC PiN rectifiers exhibiting >95% of the avalanche rating and 115 V/μm. This is one of a few reports on > 15 kV blocking voltages measured on any single semiconductor device, and the highest percentage of the avalanche limit ever reported on devices fabricated on > 100 μm thick SiC epilayers. Excellent stability of on-state voltage drop (VF) is displayed by 5.76 mm2 and large-area, 41 mm2 PiN rectifiers, when continually biased at high current densities for several days. The impact of carrier lifetime on the device performance for SiC bipolar devices with ultra-thick (≥100 μm) base layers is investigated by comparing I-V-T characteristics of SiC PiN rectifiers fabricated on 100 μm and 130 μm thick epilayers.
{"title":"15 kV SiC PiN diodes achieve 95% of avalanche limit and stable long-term operation","authors":"S. Sundaresan, M. Marripelly, Svetlana Arshavsky, R. Singh","doi":"10.1109/ISPSD.2013.6694474","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694474","url":null,"abstract":"This paper reports on ultra-high voltage, >15 kV SiC PiN rectifiers exhibiting >95% of the avalanche rating and 115 V/μm. This is one of a few reports on > 15 kV blocking voltages measured on any single semiconductor device, and the highest percentage of the avalanche limit ever reported on devices fabricated on > 100 μm thick SiC epilayers. Excellent stability of on-state voltage drop (VF) is displayed by 5.76 mm2 and large-area, 41 mm2 PiN rectifiers, when continually biased at high current densities for several days. The impact of carrier lifetime on the device performance for SiC bipolar devices with ultra-thick (≥100 μm) base layers is investigated by comparing I-V-T characteristics of SiC PiN rectifiers fabricated on 100 μm and 130 μm thick epilayers.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125545087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes an IGBT-based full-integrated power module (FIPM) that we have newly developed for compactness, high performance and low cost motor drive applications. It integrates all necessary power and control components to form a motor control system for the inverter air conditioner. Inside the FIPM there are a copper-dielectric-aluminum (CDA) substrate and a printed circuit board (PCB) substrate. All the power components such as the IGBTs and the freewheeling diodes (FWDs) are soldered directly on the CDA substrate, while the low power components such as the gate drivers, the micro control unit (MCU) and the passive components are assembled on the PCB substrate, which offers significant flexibility in the circuit layout. With this type of structure, the switching noise of the power devices that coupling to the gate drivers are effectively prevented. The electrical performance is improved by utilizing trench gate non-punch through (NPT) IGBTs which matched with its anti-parallel FWDs. Additionally, the reliability of the FIPM is further enhanced by using the aluminum layer double-sided oxidizing technology of the CDA substrate. Moreover, a large reduction of the junction to case thermal resistance of this FIPM is achieved by utilizing the half-molded resin package technology, which is especially suitable for the high power applications that need extremely good heat conductivity.
{"title":"Full-Integrated power module for motor drive applications","authors":"Qing Hua, Zehong Li, Bo Zhang, Weizhong Chen, Xiangjun Huang, Dekai Cheng","doi":"10.1109/ISPSD.2013.6694466","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694466","url":null,"abstract":"This paper proposes an IGBT-based full-integrated power module (FIPM) that we have newly developed for compactness, high performance and low cost motor drive applications. It integrates all necessary power and control components to form a motor control system for the inverter air conditioner. Inside the FIPM there are a copper-dielectric-aluminum (CDA) substrate and a printed circuit board (PCB) substrate. All the power components such as the IGBTs and the freewheeling diodes (FWDs) are soldered directly on the CDA substrate, while the low power components such as the gate drivers, the micro control unit (MCU) and the passive components are assembled on the PCB substrate, which offers significant flexibility in the circuit layout. With this type of structure, the switching noise of the power devices that coupling to the gate drivers are effectively prevented. The electrical performance is improved by utilizing trench gate non-punch through (NPT) IGBTs which matched with its anti-parallel FWDs. Additionally, the reliability of the FIPM is further enhanced by using the aluminum layer double-sided oxidizing technology of the CDA substrate. Moreover, a large reduction of the junction to case thermal resistance of this FIPM is achieved by utilizing the half-molded resin package technology, which is especially suitable for the high power applications that need extremely good heat conductivity.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126963944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694400
A. Shorten, W. Ng, M. Sasaki, T. Kawashima, H. Nishio
In this paper, a segmented IGBT gate driver IC for mitigating IGBT turn-on IC over-shoot is presented. The proposed IC is fabricated using TSMC's 0.18 μm BCD Gen-2 process. Unlike existing IC over-shoot reduction techniques, the proposed technique does not require significant additional external components or an increase in turn-on energy. During turn-on, the gate driver is controlled such that (dVGE/dt) is kept low as current is transferred from the FWD to the IGBT and kept high at all other times. The ideal timing of (dVGE/dt) transitions could vary between IGBT devices, age, temperature, etc. A feedback system is used to correct for these variances. A 37% reduction in IC overshoot is achieved while maintaining the same EON. A 54% reduction in EON is achieved for the same IC overshoot. Finally, a 15.5 dBm reduction in CEMI is observed when compared to operation with a constant ROUT and similar Eon.
{"title":"A segmented gate driver IC for the reduction of IGBT collector current over-shoot at turn-on","authors":"A. Shorten, W. Ng, M. Sasaki, T. Kawashima, H. Nishio","doi":"10.1109/ISPSD.2013.6694400","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694400","url":null,"abstract":"In this paper, a segmented IGBT gate driver IC for mitigating IGBT turn-on I<sub>C</sub> over-shoot is presented. The proposed IC is fabricated using TSMC's 0.18 μm BCD Gen-2 process. Unlike existing I<sub>C</sub> over-shoot reduction techniques, the proposed technique does not require significant additional external components or an increase in turn-on energy. During turn-on, the gate driver is controlled such that (dV<sub>GE</sub>/dt) is kept low as current is transferred from the FWD to the IGBT and kept high at all other times. The ideal timing of (dV<sub>GE</sub>/dt) transitions could vary between IGBT devices, age, temperature, etc. A feedback system is used to correct for these variances. A 37% reduction in I<sub>C</sub> overshoot is achieved while maintaining the same E<sub>ON</sub>. A 54% reduction in E<sub>ON</sub> is achieved for the same I<sub>C</sub> overshoot. Finally, a 15.5 dBm reduction in CEMI is observed when compared to operation with a constant R<sub>OUT</sub> and similar Eon.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114288962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694444
Junji Cheng, Xingbi Chen
A novel low-side structure based on the optimum variation lateral doping (OPTVLD) technique, which is formed by many inner VDMOS cells combining an outermost LDMOS, is realized in the 0.8μm BiCMOS-compatible technology. With the benefit of the additional vertical cells, it presents a low specific on-resistance with high breakdown voltage, which significantly advances the prior art. Furthermore, since this low-side structure is capable of being integrated with high-side structure and circuits on a single chip, through the low-cost self-isolation (SI) technology, it is very attractive for fabricating the smart power IC (SPIC) better and cheaper.
{"title":"A novel low-side structure for OPTVLD-SPIC technologically compatible with BiCMOS","authors":"Junji Cheng, Xingbi Chen","doi":"10.1109/ISPSD.2013.6694444","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694444","url":null,"abstract":"A novel low-side structure based on the optimum variation lateral doping (OPTVLD) technique, which is formed by many inner VDMOS cells combining an outermost LDMOS, is realized in the 0.8μm BiCMOS-compatible technology. With the benefit of the additional vertical cells, it presents a low specific on-resistance with high breakdown voltage, which significantly advances the prior art. Furthermore, since this low-side structure is capable of being integrated with high-side structure and circuits on a single chip, through the low-cost self-isolation (SI) technology, it is very attractive for fabricating the smart power IC (SPIC) better and cheaper.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122176512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694428
T. Miyoshi, T. Tominari, Y. Hayashi, T. Oshima, S. Wada, J. Noguchi
The reliability of high performance Field-PMOS FET with thick gate oxide was improved. By reducing the amount of charge in the insulating film, RESURF effect was well performed in the drift region to obtain BVDSS over 350 V. Gate oxide breakdown voltage was found to decrease at AC high slew rate, and its reduction was suppressed with the fluorine termination. NBTI shift was also reduced within 15% in a product lifetime. The fluorine termination works as suppressing parasitic charge traps effect in the oxide.
{"title":"Reliability improvement in field-MOS FETs with thick gate oxide for 300-V applications","authors":"T. Miyoshi, T. Tominari, Y. Hayashi, T. Oshima, S. Wada, J. Noguchi","doi":"10.1109/ISPSD.2013.6694428","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694428","url":null,"abstract":"The reliability of high performance Field-PMOS FET with thick gate oxide was improved. By reducing the amount of charge in the insulating film, RESURF effect was well performed in the drift region to obtain BVDSS over 350 V. Gate oxide breakdown voltage was found to decrease at AC high slew rate, and its reduction was suppressed with the fluorine termination. NBTI shift was also reduced within 15% in a product lifetime. The fluorine termination works as suppressing parasitic charge traps effect in the oxide.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126667168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694399
Lulu Peng, Rongxiang Wu, Xiangming Fang, Y. Toyoda, Masashi Akahane, M. Yamaji, H. Sumida, J. Sin
In this paper, a novel 3D TSV (Through-Silicon-Via) transformer technology for power system-on-chip applications is proposed and demonstrated experimentally. The transformer used in the power system features a galvanic isolation of > 4 kV and a voltage gain of > -3 dB from 10 MHz to 100 MHz. It can be embedded in the bottom layer of a silicon substrate and sandwiched between system circuitries for ultimate area efficiency and the smallest possible form factor compared with other conventional on-silicon approaches. A digital isolator gate driver built using this transformer technology is achieved, and successful signal transfer is clearly illustrated.
{"title":"A novel 3D TSV transformer technology for digital isolator gate driver applications","authors":"Lulu Peng, Rongxiang Wu, Xiangming Fang, Y. Toyoda, Masashi Akahane, M. Yamaji, H. Sumida, J. Sin","doi":"10.1109/ISPSD.2013.6694399","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694399","url":null,"abstract":"In this paper, a novel 3D TSV (Through-Silicon-Via) transformer technology for power system-on-chip applications is proposed and demonstrated experimentally. The transformer used in the power system features a galvanic isolation of > 4 kV and a voltage gain of > -3 dB from 10 MHz to 100 MHz. It can be embedded in the bottom layer of a silicon substrate and sandwiched between system circuitries for ultimate area efficiency and the smallest possible form factor compared with other conventional on-silicon approaches. A digital isolator gate driver built using this transformer technology is achieved, and successful signal transfer is clearly illustrated.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124000670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694447
Sunglyong Kim, Jongjib Kim, Sunhak Lee, Hyemi Kim
A new concept to realize the usage of a high-voltage bootstrap diode without substrate leakage current for 120 V high-side-driver application is proposed and verified by 2D simulation. The combination of high-voltage (HV) JFET and medium-voltage (MV) diode with proper modification to avoid substrate leakage current at forward conduction state and high-blocking voltage at off state for integrated bootstrap operation is proposed. Simulation results showed 130 V of breakdown voltage and 0.79 V of FVD (forward voltage drop) @ 100 A/cm2 without substrate leakage current at conduction mode.
{"title":"JFET pinched bootstrap diode (JPBD) without substrate leakage current integration to 120V BCDMOS process","authors":"Sunglyong Kim, Jongjib Kim, Sunhak Lee, Hyemi Kim","doi":"10.1109/ISPSD.2013.6694447","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694447","url":null,"abstract":"A new concept to realize the usage of a high-voltage bootstrap diode without substrate leakage current for 120 V high-side-driver application is proposed and verified by 2D simulation. The combination of high-voltage (HV) JFET and medium-voltage (MV) diode with proper modification to avoid substrate leakage current at forward conduction state and high-blocking voltage at off state for integrated bootstrap operation is proposed. Simulation results showed 130 V of breakdown voltage and 0.79 V of FVD (forward voltage drop) @ 100 A/cm2 without substrate leakage current at conduction mode.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"280 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-26DOI: 10.1109/ISPSD.2013.6694412
Jongseob Kim, Sun-Kyu Hwang, I. Hwang, Hyoji Choi, S. Chong, Hyun-Sik Choi, W. Jeon, Hyuk Soon Choi, Jun Yong Kim, Y. Park, K. Kim, Jong-bong Park, J. Ha, Kiyeol Park, Jae-joon Oh, J. Shin, U. Chung, I. Yoo, Kinam Kim
In this paper, we present high threshold voltage, low on-resistance, and high speed GaN-HEMT devices using a p-GaN layer in the gate stack. There are three novel features - first, for the first time, p-GaN gate HEMTs were fabricated on a 200-mm GaN on Si substrate using a Au-free fully CMOS-compatible process. Second, good electrical characteristics, including a threshold voltage of higher than 2.8 V, a low gate leakage current, no hysteresis, and fast switching, were obtained by employing a p-GaN and W gate stack. Finally, TO-220 packaged p-GaN gate HEMT devices, which can sustain a gate bias of up to 20 V, were demonstrated. Such properties indicate that our p-GaN HEMT devices are compatible with the conventional gate drivers for Si power devices.
{"title":"High threshold voltage p-GaN gate power devices on 200 mm Si","authors":"Jongseob Kim, Sun-Kyu Hwang, I. Hwang, Hyoji Choi, S. Chong, Hyun-Sik Choi, W. Jeon, Hyuk Soon Choi, Jun Yong Kim, Y. Park, K. Kim, Jong-bong Park, J. Ha, Kiyeol Park, Jae-joon Oh, J. Shin, U. Chung, I. Yoo, Kinam Kim","doi":"10.1109/ISPSD.2013.6694412","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694412","url":null,"abstract":"In this paper, we present high threshold voltage, low on-resistance, and high speed GaN-HEMT devices using a p-GaN layer in the gate stack. There are three novel features - first, for the first time, p-GaN gate HEMTs were fabricated on a 200-mm GaN on Si substrate using a Au-free fully CMOS-compatible process. Second, good electrical characteristics, including a threshold voltage of higher than 2.8 V, a low gate leakage current, no hysteresis, and fast switching, were obtained by employing a p-GaN and W gate stack. Finally, TO-220 packaged p-GaN gate HEMT devices, which can sustain a gate bias of up to 20 V, were demonstrated. Such properties indicate that our p-GaN HEMT devices are compatible with the conventional gate drivers for Si power devices.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131455368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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