Daeik D. Kim, Jonghae Kim, Choongyeun Cho, J. Plouchart, R. Trzcinski
{"title":"65nm SOI CMOS SoC Technology for Low-Power mmWave and RF Platform","authors":"Daeik D. Kim, Jonghae Kim, Choongyeun Cho, J. Plouchart, R. Trzcinski","doi":"10.1109/SMIC.2008.18","DOIUrl":null,"url":null,"abstract":"An RF and mm-wave platform developed in 65 nm SOI CMOS technology is presented. The SOI FET performance in a wired cell is measured up to fT=300 GHz and 200 GHz for NFET and PFET. Ring oscillator records 3.6 psec minimum inverter stage delay. Back-end-of-line vertical native capacitor (VNCAP) and on-chip inductor performances are reported. The performance scaling trends of mmWave PLL front-end components are presented.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"115 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMIC.2008.18","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An RF and mm-wave platform developed in 65 nm SOI CMOS technology is presented. The SOI FET performance in a wired cell is measured up to fT=300 GHz and 200 GHz for NFET and PFET. Ring oscillator records 3.6 psec minimum inverter stage delay. Back-end-of-line vertical native capacitor (VNCAP) and on-chip inductor performances are reported. The performance scaling trends of mmWave PLL front-end components are presented.