3D interconnection and packaging: impending reality or still a dream?

E. Beyne
{"title":"3D interconnection and packaging: impending reality or still a dream?","authors":"E. Beyne","doi":"10.1109/ISSCC.2004.1332632","DOIUrl":null,"url":null,"abstract":"Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"70","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332632","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 70

Abstract

Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).
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3D互联与封装:即将成为现实还是梦想?
传统的互连方案基本上是二维的。能够将多个集成电路在三维空间中连接起来,是系统设计者长久以来的梦想。本文描述了三种解决3D互连问题的方法:系统级封装(3D- sip)、系统级芯片(3D- soc)和3D集成电路(3D- ic)。
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