{"title":"Design and implementation of a multiprocessor with hypercube interconnection network","authors":"M. Nagata, S. Fukuda, K. Kihara","doi":"10.1109/IECON.1989.69727","DOIUrl":null,"url":null,"abstract":"The authors present the design and implementation of a multiprocessor with a hypercube interconnection network. The hardware configuration of the hypercube multiprocessor is realized by using 16 processing elements (PEs) with a single CPU and five parallel interfaces per PE. Four programmable parallel interfaces (PPI) are interconnected with four adjacent PEs in a hypercube manner, and the other PPI is directly connected to the control computer. The software structure is also presented, focusing on the communication mechanism between adjacent PEs of the hypercube multiprocessor and communication between the PE and the control computer. Furthermore, the implemented graphic display control and its interface are briefly described from the viewpoint of hardware. The designed system has wide applicability in parallel computation with load balancing among PEs of the hypercube multiprocessor.<<ETX>>","PeriodicalId":384081,"journal":{"name":"15th Annual Conference of IEEE Industrial Electronics Society","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th Annual Conference of IEEE Industrial Electronics Society","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IECON.1989.69727","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The authors present the design and implementation of a multiprocessor with a hypercube interconnection network. The hardware configuration of the hypercube multiprocessor is realized by using 16 processing elements (PEs) with a single CPU and five parallel interfaces per PE. Four programmable parallel interfaces (PPI) are interconnected with four adjacent PEs in a hypercube manner, and the other PPI is directly connected to the control computer. The software structure is also presented, focusing on the communication mechanism between adjacent PEs of the hypercube multiprocessor and communication between the PE and the control computer. Furthermore, the implemented graphic display control and its interface are briefly described from the viewpoint of hardware. The designed system has wide applicability in parallel computation with load balancing among PEs of the hypercube multiprocessor.<>
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