{"title":"The mapping of an adaptive robot control algorithm onto RM, a reconfigurable machine for highly parallel real-time applications","authors":"S. Erdogan, E.T. Tunali, N. Kuo","doi":"10.1109/RTA.1993.263106","DOIUrl":null,"url":null,"abstract":"The paper describes a configuration of the reconfigurable machine (RM) specifically optimized to handle inverse dynamics computation for robot control and to implement a neural network control strategy in a parallel platform. The difficulties of operating on a reconfigurable platform are overcome by defining a fixed processing element (PE) model with multiple processing components and by using the PE's local memory for storing micro-instructions to drive the parallel processors. Traditionally, reconfigurable platforms have been used to contain all the execution sequences and a local memory is usually provided to store the necessary data. VHDL description of the model has been used for simulation, synthesis and optimization for mapping to XILINX 4005 FPGA technology.<<ETX>>","PeriodicalId":293622,"journal":{"name":"[1993] Proceedings of the IEEE Workshop on Real-Time Applications","volume":"589 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993] Proceedings of the IEEE Workshop on Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTA.1993.263106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The paper describes a configuration of the reconfigurable machine (RM) specifically optimized to handle inverse dynamics computation for robot control and to implement a neural network control strategy in a parallel platform. The difficulties of operating on a reconfigurable platform are overcome by defining a fixed processing element (PE) model with multiple processing components and by using the PE's local memory for storing micro-instructions to drive the parallel processors. Traditionally, reconfigurable platforms have been used to contain all the execution sequences and a local memory is usually provided to store the necessary data. VHDL description of the model has been used for simulation, synthesis and optimization for mapping to XILINX 4005 FPGA technology.<>