{"title":"Digitally programmable DC-DC voltage down converter","authors":"M. Lin, H. Lin, C. Chen, S. Jou","doi":"10.1109/APASIC.1999.824109","DOIUrl":null,"url":null,"abstract":"This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-/spl mu/m triple-metal CMOS process on 1000/spl times/1000 /spl mu/m/sup 2/ core size. The simulation results show that it can convert +5 V input voltage to +2/spl sim/+5 V output voltage in the 50 /spl mu/s settling time.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824109","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-/spl mu/m triple-metal CMOS process on 1000/spl times/1000 /spl mu/m/sup 2/ core size. The simulation results show that it can convert +5 V input voltage to +2/spl sim/+5 V output voltage in the 50 /spl mu/s settling time.
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