Detection of SRAM cell stability by lowering array supply voltage

D. Kwai, Hung-Wen Chang, H. Liao, Ching-Hua Chiao, Yung-Fa Chou
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引用次数: 26

Abstract

In this paper, we discuss a design-for-test technique for the detection of cell stability in static random access memory (SRAM). The power supply to the memory array is isolated and independently accessible from an external terminal. By lowering the array supply voltage, the cell stability is degraded, making the defective cells susceptible to noises induced by read/write operations. On-silicon characterization result using 0.18 /spl mu/m CMOS technology is reported. It shows that the weak tailing bits in the statistical distribution can manifest themselves. The implementation of the test mode is inherently low-cost and can be combined with previously proposed methods for an improved detection capability.
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降低阵列供电电压检测SRAM电池稳定性
本文讨论了一种用于静态随机存取存储器(SRAM)中单元稳定性检测的测试设计技术。存储阵列的电源是隔离的,并且可以从外部端子独立地访问。通过降低阵列供电电压,降低了电池的稳定性,使有缺陷的电池容易受到读写操作引起的噪声的影响。报道了采用0.18 /spl μ m CMOS技术的硅上表征结果。结果表明,统计分布中的弱尾位是可以表现出来的。测试模式的实现具有固有的低成本,并且可以与先前提出的方法相结合,以提高检测能力。
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