Multilayered neural network implementation on transputer systolic array

Q. Song, E.K. Teoh, D.P. Mital
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引用次数: 2

Abstract

Performance analysis and comparison are carried out for the one- and two-dimensional systolic arrays based on transputers. Low efficiency has been found in the one-dimensional array because of communication overhead. The systolic algorithm is extended to the two-dimensional array to implement a full parallelism in each layer's calculation. This speeds up simulation of the network. Experiment results are provided to support the performance evaluation.

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基于转发器收缩阵列的多层神经网络实现
对基于转发器的一维和二维收缩阵列进行了性能分析和比较。由于通信开销的影响,一维阵列的效率很低。将收缩算法扩展到二维数组中,实现了每层计算的完全并行化。这加快了网络模拟的速度。实验结果为性能评价提供了依据。
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