Microprocessing and Microprogramming最新文献

In this paper an extended Petri net, the programmable logic controller net (PLCNet) is defined. A rule-based PLCNet simulator has been designed based on the semantics of PLCNets, with facilities provided to set up and control simulation. Both step and time responses are provided for the presentation of simulation results. A graphical environment is provided for the construction of the PLCNet, simulation and the presentation of simulation results.

We propose a new scheme for the replacement of cache lines in high performance computer systems. Preliminary research, to date, indicates that neural networks (NNs) have great potential in the area of statistical predictions [1]. This attribute of neural networks is used in our work to develop a neural network-based replacement policy which can effectively eliminate dead lines from the cache memory by predicting the sequence of memory addresses referenced by the central processing unit (CPU) of a computer system. The proposed strategy may, therefore, provide better cache performance as compared to the conventional schemes, such as: LRU (Least Recently Used), FIFO (First In First Out), and MRU (Most Recently Used) algorithms. In fact, we observed from the simulation experiments that a carefully designed neural network-based replacement scheme does provide excellent performance as compared to the LRU scheme. The new approach can be applied to the page replacement and prefetching algorithms in virtual memory systems.

Some mathematical CAD packages are inadequate in computing the composite functions involving the product of an exponential function and an error function complement. These functions arise in physical applications, such as problems in diffusion. Their importance warrants a composite treatment. If their component factors are computed individually, discontinuities in the evaluations arises, as shown in some CAD packages. An improved algorithm is presented which overcomes this deficiency, and provides a fast evaluation. Such evaluation is successful even using floating point numbers with single precision. The potential for numerical overflow associated with large arguments has been overcome.

This paper presents a hybrid approach to distributed mutual exclusion in which two algorithms are combined such that one minimizes message traffic and the other minimizes time delay. In a hybrid approach, sites are divided into groups, and two different algorithms are used to resolve local (intra-group) and global (inter-group) conflicts. In this paper, we develop a hybrid distributed mutual exclusion algorithm which uses Singhal's dynamic information structure algorithm [15] as the local algorithm to minimize time delay and Maekawa's algorithm [7] as the global algorithm to minimize message traffic. Compared to Maekawa's algorithm which needs O(√N) messages, but two time units delay between successive executions of the Critical Section (CS) (where N is the number of sites in the system), the proposed hybrid algorithm can reduce message traffic by 52% and time delay by 29% at the same time.

We examine the efficient implementation of back-propagation (BP) type algorithms on TO [3], a vector processor with a fixed-point engine, designed for neural network simulation. Using Matrix Back Propagation (MBP) [2]we achieve an asymptotically optimal performance on TO (about 0.8 GOPS) for both forward and backward phases, which is not possible with the standard on-line BP algorithm. We use a mixture of fixed- and floating-point operations in order to guarantee both high efficiency and fast convergence. Though the most expensive computations are implemented in fixed-point, we achieve a rate of convergence that is comparable to the floating-point version. The time taken for conversion between fixed- and floating-point is also shown to be reasonably low.

A parallel simulation tool has been developed with the aim of evaluating the performance of a class of ATM switching systems. In this paper, the class of ATM switching networks of interest and the corresponding modelling are addressed. An appropriate decomposition scheme is revealed with respect to the model being built. The performance of the parallel tool is examined, based on a scalable ATM switching network, by means of a loosely-coupled parallel computer system. A combination of general purpose and problem specific algorithms results in a high computational efficiency, portability and scalability.

The paper considers a development of the conversation scheme version proposed by A. Clematis and V. Gianuzzi in Microprocessing and Microprogramming (Vol. 32, No. 1–5, 1991) [5] and Computer Languages (Vol. 18, No. 3, 1993) [6]. The authors discussed the methodology of using conversations within a conventional concurrent language (Ada), which makes the conversation scheme practical. In our paper we concentrate on the improvements for their scheme. We believe that it is important for the programmer to have more choice, and propose what could be called a library of schemes from which the appropriate scheme could be chosen depending on the application. We discuss ways of setting dynamically the number of processes participating in a conversation; of having different sets of servers involved in different alternates of the same conversation; of introducing a global acceptance test which would be more sophisticated; of increasing robustness of the conversation. All of these proposals are meant to be used within a conventional language.