Performance Enhancement Of Cmos Terahertz Detector

Abstract

For improving the performance of CMOS terahertz detectors, parasitic capacitance reduction technique and new working model are proposed for MOSFET devices. We investigate the influence of source parasitic capacitance and drain-to-source current on the performance of CMOS terahertz detectors and analyze the relationship to the voltage responsivity $(\mathrm{R}_{V})$ and noise equivalent power (NEP) of detectors. Experiment on the CMOS detectors with a 650GHz antenna shows the maximum improvement of voltage responsivity can attain to 155% by suppressing gate-source parasitic capacitance. The additional drain current Ids can further increase RV while NEP remains unchanged.