Haesoo Kim, Kangbin Lee, K. Han, Seokwon Cho, Se Kyoung Choi, S. Seo, J. Chung, K. Lee, Sungjae Chung, K. Noh, Tae-Un Youn, Ju Yeab Lee, Min Kyu Lee, B. Han, S. M. Yi, H. Lee, Sung Soon Kim, W. S. Shin, K. Yun, M. Ko, J. Choi, Sang Wan Lee, Sang Deok Kim, Myung Kyu Ahn, Ki Seog Kim, Y. Jeon, Sung Kye Park, S. Aritome, Jin Woong Kim, Sang Sun Lee, S. Lee, K. Ahn, Sung-Joo Hong, G. Bae, S. Park
{"title":"Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability","authors":"Haesoo Kim, Kangbin Lee, K. Han, Seokwon Cho, Se Kyoung Choi, S. Seo, J. Chung, K. Lee, Sungjae Chung, K. Noh, Tae-Un Youn, Ju Yeab Lee, Min Kyu Lee, B. Han, S. M. Yi, H. Lee, Sung Soon Kim, W. S. Shin, K. Yun, M. Ko, J. Choi, Sang Wan Lee, Sang Deok Kim, Myung Kyu Ahn, Ki Seog Kim, Y. Jeon, Sung Kye Park, S. Aritome, Jin Woong Kim, Sang Sun Lee, S. Lee, K. Ahn, Sung-Joo Hong, G. Bae, S. Park","doi":"10.1109/VLSI-TSA.2012.6210120","DOIUrl":null,"url":null,"abstract":"We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell Vt distribution are drastically improved. These technologies play an important role in the characteristic of scaled NAND flash memory cell and reliability.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2012.6210120","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell Vt distribution are drastically improved. These technologies play an important role in the characteristic of scaled NAND flash memory cell and reliability.
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