A low-power CMOS pipeline ADC using multiple sharing technique for ZigBee transceiver

Abstract

A 10bit, 20MS/s pipeline ADC is proposed for ZigBee transceiver in this paper. Due to demand of low power, a multiple sharing technique involved operational operational amplifier (opamp) and comparator is proposed, traditional S/H circuit is cancelled, a new gain boosting switch which could achieve sample and hold in first stage is also proposed. Implemented in a 0.18μm CMOS process, only 19.6mW power consumption from 1.8V power supply is achieved. SNR and SFDR are 61.5dB and 66.24dB, respectively, when a 1MS/s sinusoid signal inputs to the ADC at 20MS/s sampling rate. Particularly the test results show this pipeline ADC is suitable for a low power consumption ZigBee system.