Verification of memory transactions in AXI protocol using system verilog approach

Abstract

This paper mainly focuses on verifying the important features of advanced extensible interface (AXI). Verifying the memory transactions of AXI includes the verification of all the five channels write address, write data, write response, read address and read data. In this work a Verification Intellectual Property cores (VIP) based methodology is used to carry out the verification Process. In the VIP design the entire test environment is modeled using system verilog and the read, write transactions from the same and different memory locations has been verified with the quantitative values of Busy Count, Valid Count and its Bus Utilization. Verifying the System connectivity during write and read cycles is also one of the fundamental features verified in this paper.