Channel strain engineering for high performance CMOS technology

Abstract

▪ Longitudinal compressive stress in the GPa regime is required for the 45nm SOI high-performance pFET device to meet aggressive performance goals. ▪ Compressive stress liner, and eSiGe stressor enhancement was employed in order to achieve a 1.6 GPa channel stress level. ▪ Mobility enhancement of the 45nm baseline device is shown to be 4X-fold higher than relaxed-Si. Effective piezo-cofficients extracted for wide range of stress highlighting 3 stress regimes. Stress and drive current are shown to be correlated with a coefficient equal to ∼ 0.25. ▪ Low-field mobility is shown to be strongly correlated to injection velocity. High strain pFET devices with gate length down to 35nm operate at about 60% of the thermal limit. ▪ Challenge for future technology nodes- the mobility vs stress relationship for channel stress levels in the 1.6GPa regime is approaching saturation. To continue this incredible rate of performance increase (17%/year), methods of increasing the low-field mobility through increased thermal velocity is required.