A CRC-Based Concurrent Fault Detection Architecture for Galois/Counter Mode (GCM)

Abstract

The Galois/Counter Mode (GCM) is a recently adopted mode of operation for symmetric key cryptography to provide both data authenticity and confidentiality. To improve the reliability of hardware implementations of the GCM module, we propose a novel multiple-bit fault detection architecture for hardware implementation of the GCM module using cyclic redundancy check (CRC) codes. By changing the degree of the CRC generating polynomial, one can select the number of parity bits used in the fault detection scheme based on the available resources and required overheads. We derive new formulations for the corresponding fault-detection scheme for the entire GCM loop. Then, we provide FPGA implementation and fault coverage simulation results for different CRC generating polynomials. We show that using six parity bits, one can achieve high fault coverage of close to 100% with the critical path delay overhead of 23% and area overhead of 10.9% while the false alarm is 0.12%.