New distributed controlling architecture for high performances NAND generation

Abstract

This paper describes the controlling architecture changes introduced in the last generation of NAND flash. The pressing demand for performance from NAND systems required an increase in the working frequencies and task parallelism of the logical executors. In the new controller generation, the algorithm execution has been distributed creating a controlling hierarchy formed by a central executor which performs the main flow and the complex calculations at low frequency, to save power, supported by small but fast machines, placed near the slower peripherals. These machines, called HW (HardWare) accelerators, drive slower peripherals at high speed and in parallel with main flow to increase performances, but are launched only on request to avoid important power impacts. The new architecture proposed in this work, allowed to deliver an outstanding tprog effective on new generation devices, opening a path to even more aggressive tprog in the future with newly identified optimizations. These techniques are in practice on products currently in production.