{"title":"Temperature dependent universal hole and electron mobility models for CMOS circuit simulation","authors":"K. Min, K. Lee","doi":"10.1109/TENCON.1995.496375","DOIUrl":null,"url":null,"abstract":"Semi-empirical universal hole and electron mobility models with temperature dependence have been proposed for circuit simulation as well as for process characterization. These models are based on the universal dependence of low field mobility on the effective transverse field and cover a wide range of oxide thickness as well as of temperature. The accuracy of our models is justified by comparison with experimental work reported in the literature and obtained in our laboratory. The models are accurate and physical enough to be suited for simulation of modern VLSI CMOS circuits with gate oxide thickness less than 400 /spl Aring/ in the temperature range of 250-400 K.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.1995.496375","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Semi-empirical universal hole and electron mobility models with temperature dependence have been proposed for circuit simulation as well as for process characterization. These models are based on the universal dependence of low field mobility on the effective transverse field and cover a wide range of oxide thickness as well as of temperature. The accuracy of our models is justified by comparison with experimental work reported in the literature and obtained in our laboratory. The models are accurate and physical enough to be suited for simulation of modern VLSI CMOS circuits with gate oxide thickness less than 400 /spl Aring/ in the temperature range of 250-400 K.