Three dimensional steady-state temperature prediction of volumetric heating sources embedded into multi-layer electronic board substrate

Abstract

Burying active chips into internal layers of a Printed Wiring Board (PWB) allows increasing the density of an electronic board but leads to higher thermal stress inside its structure. To help the designers for analyzing the limits of the in-layer power dissipation, various analytical approaches were investigated. So the present work focuses on the thermal model based on a three anisotropic layers. The active chips are assumed as planar or volumetric heat sources. These assumptions are compared to a state-of-art numerical model which details all PWB layers. As expected the accuracy is depending of the geometrical representation of the source. Thus, the planar-source model is within ±16% of relative error with the numerical results when volumetric-source model is ±8%. Nevertheless, both source-models demonstrate their high capability to quickly predict the thermal behavior of embedded chips placements. Moreover, the three-dimensional representation of the chip is discussed in terms of computation effort.