Low Cost FPGA Implementation of a SPI over High Speed Optical SerDes

Abstract

Serial Peripheral Interface (SPI) is a commonly used communication protocol that allows serial data transfer between a master and a slave device over a short distance. However, if we require just SPI over long distances currently there is no effective low-cost solution. A SerDes provides a solution to this shortcoming by sending parallel data as a serial transmission and converting it back at the receiver end. However, most of the current SerDes implementations are expensive to implement and cater to very high-speed applications, which is not the case in SPI. In this paper, we present a simple to implement and low cost SerDes solution for sending and receiving multiple SPI and GPIO lines. Our proposed solution makes use of a low cost CLPD / FPGA and is applicable for low data rate applications such as SPI. This paper investigates the simplest solution to the problem, whilst maintaining a reliable single wire / optical link. For testing, we have implemented three novel encoding schemes that all provided good results, each measured by performance against resource usage. One of these encoding schemes has shown a drop-out rate as low as 0.001% over a 24-hour period. Our proposed solution when used in conjunction with an optical fibre medium could potentially allow SPI transmission over several kilometres of distance.