Pub Date : 2019-03-01DOI: 10.1109/SPIN.2019.8711640
Hiranya Ranjan Thakur, Gaurav Keshwani, J. Dutta
This work explores the feasibility of electrochemical deposition (ECD) of zirconia on ITO coated glass. The thickness and morphology of the zirconia layers are very much affected by the process conditions such as temperature, working electrode potential, current density, deposition time and properties of the solvent. The effect of these factors on the quality of the layers formed has been considered in detail in this paper. Zirconia films (ZrO2) of different thickness have been deposited electrochemically on ITO coated glass. Experiments have been carried out in aqueous and non-aqueous electrolyte solution of zirconium tetra chloride (ZrCl4) at different temperatures. The thickness of the deposited layers varied within the range of 35–256 nm. The formation of stoichiometric layer of ZrO2 has been confirmed by X-ray diffraction and SEM results.
{"title":"Characterization of Thin Zirconia Films Deposited by ECD on ITO Coated Glass for Biosensing Applications","authors":"Hiranya Ranjan Thakur, Gaurav Keshwani, J. Dutta","doi":"10.1109/SPIN.2019.8711640","DOIUrl":"https://doi.org/10.1109/SPIN.2019.8711640","url":null,"abstract":"This work explores the feasibility of electrochemical deposition (ECD) of zirconia on ITO coated glass. The thickness and morphology of the zirconia layers are very much affected by the process conditions such as temperature, working electrode potential, current density, deposition time and properties of the solvent. The effect of these factors on the quality of the layers formed has been considered in detail in this paper. Zirconia films (ZrO2) of different thickness have been deposited electrochemically on ITO coated glass. Experiments have been carried out in aqueous and non-aqueous electrolyte solution of zirconium tetra chloride (ZrCl4) at different temperatures. The thickness of the deposited layers varied within the range of 35–256 nm. The formation of stoichiometric layer of ZrO2 has been confirmed by X-ray diffraction and SEM results.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128186041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. P. Chaudhari, Jani Babu Shaik, S. Singhal, Nilesh Goel
Static metrics are often used to characterize read stability and write-ability of an SRAM cell. In this paper, two major dynamic SRAM metrics: critical read stability (TREAD) and critical writeability (TWRITE) are discussed and correlated with static metrics. For correlation between dynamic and static metrics, variability analysis is carried out at time-zero and after NBTI degradation of the SRAM cell. Shift in correlation factor is compared for before and after NBTI degradation. Assessment of correlation between dynamic and static metrics is used to identify those static metrics which best capture the dynamic behavior of the cell.
{"title":"Correlation of Dynamic and Static Metrics of SRAM Cell under Time-Zero Variability and After NBTI Degradation","authors":"S. P. Chaudhari, Jani Babu Shaik, S. Singhal, Nilesh Goel","doi":"10.1109/ISES.2018.00028","DOIUrl":"https://doi.org/10.1109/ISES.2018.00028","url":null,"abstract":"Static metrics are often used to characterize read stability and write-ability of an SRAM cell. In this paper, two major dynamic SRAM metrics: critical read stability (TREAD) and critical writeability (TWRITE) are discussed and correlated with static metrics. For correlation between dynamic and static metrics, variability analysis is carried out at time-zero and after NBTI degradation of the SRAM cell. Shift in correlation factor is compared for before and after NBTI degradation. Assessment of correlation between dynamic and static metrics is used to identify those static metrics which best capture the dynamic behavior of the cell.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115425756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A simple square microhotplate with a S-Shaped heater is designed, fabricated and tested. The fabricated microhotplate operates at a temperature of 380K, with a power consumption of 306mW and a heating efficiency of 1.810–6W/µm2. Mathematical model, utilizing a new triangular approach, has been developed for predicting the power consumption of microhotplate. Triangular approach for estimating the membrane area has resulted in a smaller (<1%) area error when compared to existing strip or circular approach. The triangular approach has thus led to an accurate calculation of membrane thermal resistance and power consumption. The developed model is in close agreement (within 9%) with the experimental and FEM simulation results.
{"title":"Modeling of Square Microhotplate and its Validation with Experimental Results","authors":"G. Saxena","doi":"10.1109/ises.2018.00019","DOIUrl":"https://doi.org/10.1109/ises.2018.00019","url":null,"abstract":"A simple square microhotplate with a S-Shaped heater is designed, fabricated and tested. The fabricated microhotplate operates at a temperature of 380K, with a power consumption of 306mW and a heating efficiency of 1.810–6W/µm2. Mathematical model, utilizing a new triangular approach, has been developed for predicting the power consumption of microhotplate. Triangular approach for estimating the membrane area has resulted in a smaller (<1%) area error when compared to existing strip or circular approach. The triangular approach has thus led to an accurate calculation of membrane thermal resistance and power consumption. The developed model is in close agreement (within 9%) with the experimental and FEM simulation results.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115084471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dhirendra Kumar, Kasif Nabi, P. K. Misra, M. Goswami
This paper introduces design and implementation of True Random Number Generator (TRNG) based on discrete time chaos map, which uses two chaotic maps to avoid the limitation of lesser entropy generated using single chaotic map based TRNG and offset error of the current mirror as well as the mismatch of transistor for enhanced randomness. The proposed architecture is implemented considering two modified tent map (MTM) together with different design of sample and hold (S/H) and comparator circuits. The design utilizes less resources yielding hardware redundancy and also enhances the level of randomness. This TRNG have been designed and validated using 180nm CMOS technology in cadence virtuoso tool. Power dissipation and speed have been obtained as 2.4mW and 50Mbps respectively. The generated random bit stream have also been sampled and converted to binary format in MATLAB and tested through NIST 800.22 statistical test suite for validation. The proposed design pass efficiency is more than 90%.
{"title":"Modified Tent Map Based Design for True Random Number Generator","authors":"Dhirendra Kumar, Kasif Nabi, P. K. Misra, M. Goswami","doi":"10.1109/ISES.2018.00016","DOIUrl":"https://doi.org/10.1109/ISES.2018.00016","url":null,"abstract":"This paper introduces design and implementation of True Random Number Generator (TRNG) based on discrete time chaos map, which uses two chaotic maps to avoid the limitation of lesser entropy generated using single chaotic map based TRNG and offset error of the current mirror as well as the mismatch of transistor for enhanced randomness. The proposed architecture is implemented considering two modified tent map (MTM) together with different design of sample and hold (S/H) and comparator circuits. The design utilizes less resources yielding hardware redundancy and also enhances the level of randomness. This TRNG have been designed and validated using 180nm CMOS technology in cadence virtuoso tool. Power dissipation and speed have been obtained as 2.4mW and 50Mbps respectively. The generated random bit stream have also been sampled and converted to binary format in MATLAB and tested through NIST 800.22 statistical test suite for validation. The proposed design pass efficiency is more than 90%.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122484923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Mishra, Harsh Srivastava, P. K. Misra, M. Goswami
At lower technology, the static power dissipation and stability of conventional six transistors static random access memory (SRAM) cell poses a major issue. To address this issue, a novel eleven transistor (11T) SRAM cell for improving read stability and reducing the static power dissipation is proposed in this work. In the proposed 11T SRAM cell, the storing node isolates from the read bit line using separate read port while sleep transistor methodology is explored for power saving. With this the read static noise margin (RSNM) value of proposed design is enhanced by 6x, 2.3x, 2.7x and 1.3x when compared with basic 6T SRAM cell, 11T ST2 SRAM cell, 11T ST1 SRAM cell, ST11T SRAM cell respectively. The write stability is also enhanced by 1.6x over basic 6T SRAM cell, 1.14x over 11T SRAM and penalty of 1.17x when compared with other 11T SRAM cell. Further, using the sleep transistor methodology the static power consumption of the proposed design has been reduced by 4.6x when compared with basic 6T SRAM cell. The proposed 11T SRAM cell has been verified in 40nm CMOS technology node using cadence virtuoso tool.
{"title":"A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology","authors":"J. Mishra, Harsh Srivastava, P. K. Misra, M. Goswami","doi":"10.1109/ISES.2018.00011","DOIUrl":"https://doi.org/10.1109/ISES.2018.00011","url":null,"abstract":"At lower technology, the static power dissipation and stability of conventional six transistors static random access memory (SRAM) cell poses a major issue. To address this issue, a novel eleven transistor (11T) SRAM cell for improving read stability and reducing the static power dissipation is proposed in this work. In the proposed 11T SRAM cell, the storing node isolates from the read bit line using separate read port while sleep transistor methodology is explored for power saving. With this the read static noise margin (RSNM) value of proposed design is enhanced by 6x, 2.3x, 2.7x and 1.3x when compared with basic 6T SRAM cell, 11T ST2 SRAM cell, 11T ST1 SRAM cell, ST11T SRAM cell respectively. The write stability is also enhanced by 1.6x over basic 6T SRAM cell, 1.14x over 11T SRAM and penalty of 1.17x when compared with other 11T SRAM cell. Further, using the sleep transistor methodology the static power consumption of the proposed design has been reduced by 4.6x when compared with basic 6T SRAM cell. The proposed 11T SRAM cell has been verified in 40nm CMOS technology node using cadence virtuoso tool.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129540011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chetan Kamble, K. SiddharthR., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar
This work proposes a simple and efficient way of designing a Square-root Carry Select Adder (SQRT-CSLA). The transistor-level modification in the Carry Select Adder (CSLA) significantly reduces the hardware complexity and power dissipation. Based on this modification, an 8-bit, 16-bit, 32-bit and 64-bit Square-root CSLA architecture is designed. The proposed design is simulated at a transistor level in a 180 nm, CMOS technology with a supply voltage of 1.8 V. The proposed design is able to achieve 30% reduction in Power-Delay Product (PDP) compared to the existing architectures.
{"title":"Design of Area-Power-Delay Efficient Square Root Carry Select Adder","authors":"Chetan Kamble, K. SiddharthR., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar","doi":"10.1109/ises.2018.00026","DOIUrl":"https://doi.org/10.1109/ises.2018.00026","url":null,"abstract":"This work proposes a simple and efficient way of designing a Square-root Carry Select Adder (SQRT-CSLA). The transistor-level modification in the Carry Select Adder (CSLA) significantly reduces the hardware complexity and power dissipation. Based on this modification, an 8-bit, 16-bit, 32-bit and 64-bit Square-root CSLA architecture is designed. The proposed design is simulated at a transistor level in a 180 nm, CMOS technology with a supply voltage of 1.8 V. The proposed design is able to achieve 30% reduction in Power-Delay Product (PDP) compared to the existing architectures.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123387046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a compact antenna with improved gain, reduced dimension, and enhanced bandwidth for Ultra Wide Band (UWB) characteristics has been realized. The microstrip line (ML) is used to feed section of the UWB antenna followed by a semicircular patch. The ground part has inserted the combination of the rectangular and semicircular patch. This ground part gives the enhanced bandwidth and semicircular path gives the improved gain. The proposed antenna is used for radar and satellite communication system. The prototype of the antenna is fabricated and tested with a dimension of 21.6 x 12.6 x 2.54 mm3. The measured results are found to be sufficiently close with the simulation results. It has a gain of 2.625 to 6.4 dBi, impedance bandwidth of 10 GHz with a range of 2.5 to 12.5 GHz and radiation efficiency of 80-87.5 % have achieved over the band.
本文实现了一种具有提高增益、减小尺寸和增强带宽的超宽带(UWB)天线。微带线(ML)用于UWB天线的馈电部分，然后是半圆形贴片。接地部分插入了矩形和半圆形贴片的组合。该接地部分增强了带宽，半圆路径提高了增益。该天线用于雷达和卫星通信系统。天线的原型制作和测试尺寸为21.6 x 12.6 x 2.54 mm3。实测结果与仿真结果相当接近。它的增益为2.625 ~ 6.4 dBi，阻抗带宽为10 GHz，范围为2.5 ~ 12.5 GHz，在该频段内的辐射效率达到80 ~ 87.5%。
{"title":"Compact UWB Antenna for S, C, and X Bands Applications","authors":"Anil Kumar Nayak, Debasis Gountia, Baruna Kumar Turuk, Sashi Bhusan Panda","doi":"10.1109/ISES.2018.00047","DOIUrl":"https://doi.org/10.1109/ISES.2018.00047","url":null,"abstract":"In this paper, a compact antenna with improved gain, reduced dimension, and enhanced bandwidth for Ultra Wide Band (UWB) characteristics has been realized. The microstrip line (ML) is used to feed section of the UWB antenna followed by a semicircular patch. The ground part has inserted the combination of the rectangular and semicircular patch. This ground part gives the enhanced bandwidth and semicircular path gives the improved gain. The proposed antenna is used for radar and satellite communication system. The prototype of the antenna is fabricated and tested with a dimension of 21.6 x 12.6 x 2.54 mm3. The measured results are found to be sufficiently close with the simulation results. It has a gain of 2.625 to 6.4 dBi, impedance bandwidth of 10 GHz with a range of 2.5 to 12.5 GHz and radiation efficiency of 80-87.5 % have achieved over the band.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123457433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low power 5-stage current starved voltage controlled oscillator, designed at 50 MHz. For control voltage varying from 0.4 V to 1.6 V, the oscillator frequency linearly varies from 7 MHz to 105 MHz linearly. At supply voltage of 1.8 V, the circuit is low power (134 µW) in comparison to circuits reported in the literature. It exhibits a phase noise of -101.9 dBc/Hz at 1 MHz offset from 50 MHz carrier frequency. The circuit is designed in SCL 180 nm CMOS process using cadence environment.
{"title":"Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process","authors":"C. Shekhar, S. Qureshi","doi":"10.1109/ises.2018.00027","DOIUrl":"https://doi.org/10.1109/ises.2018.00027","url":null,"abstract":"This paper presents a low power 5-stage current starved voltage controlled oscillator, designed at 50 MHz. For control voltage varying from 0.4 V to 1.6 V, the oscillator frequency linearly varies from 7 MHz to 105 MHz linearly. At supply voltage of 1.8 V, the circuit is low power (134 µW) in comparison to circuits reported in the literature. It exhibits a phase noise of -101.9 dBc/Hz at 1 MHz offset from 50 MHz carrier frequency. The circuit is designed in SCL 180 nm CMOS process using cadence environment.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127982253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sonal Yadav, V. Laxmi, H. Kapoor, M. Gaur, Mark Zwolinski
Large scale chip multiprocessors employ a multi-NoC, consisting of multiple physical channels for inter-core communication. Placement of a custom arbitration logic can improve the critical path delay and relax the worst case timing closure of the network. In particular, it can effectively distribute and manage the traffic from the multi-threaded workloads among the multiple networks of the NoC. This paper gives the design and implementation of the arbitration logic at the router crossbars. The results are compared with baseline NoC and other multi-NoC architectures. The proposed energy efficient router saves up to 57% of the router power consumption.
{"title":"A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic","authors":"Sonal Yadav, V. Laxmi, H. Kapoor, M. Gaur, Mark Zwolinski","doi":"10.1109/ISES.2018.00060","DOIUrl":"https://doi.org/10.1109/ISES.2018.00060","url":null,"abstract":"Large scale chip multiprocessors employ a multi-NoC, consisting of multiple physical channels for inter-core communication. Placement of a custom arbitration logic can improve the critical path delay and relax the worst case timing closure of the network. In particular, it can effectively distribute and manage the traffic from the multi-threaded workloads among the multiple networks of the NoC. This paper gives the design and implementation of the arbitration logic at the router crossbars. The results are compared with baseline NoC and other multi-NoC architectures. The proposed energy efficient router saves up to 57% of the router power consumption.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114764192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Debajyoti Mukhopadhyay, Megha Gupta, Tahesin Attar, Prajakta S. Chavan, Vidhi S. Patel
As the amount of urban vehicle grows rapidly, vehicle theft has become a shared concern for all citizens. Security and safety have always become a necessity for urban population. However, present anti-theft systems lack the tracking and monitoring function. Internet of things(IOT) has been governing the electronics era with cloud services dominating the ever-increasing electronics product segment. Thus, there is a need to develop a system for providing security to the vehicle from problems like theft and towing using IOT for security of automobiles and passengers. Our system proposes a novel security system based on wireless communication and a lowcost Bluetooth module. This paper illustrates a model in which the GSM is used for sending messages. the user can control the engine/ignition and turn it off if needed. The system also employs a password through keypad (with maximum 3 chances) which controls the opening of a safety locker door as well as wearing of a seat belt. If there is a window intruder, the IR module/sensor detects the intruder, or any obstacle and it sends a signal to the micro controller. The controller is connected to a Bluetooth module and to an alarm system. The System transmits an alert signal to the dashboard (which is nothing but a mobile handset) which sends an alert signal to the user's mobile phone. The prototype also provides a solution to the problem like Towing. Thus, the system uses Bluetooth module and controller to control the security system from the user's mobile phone by means of any device with a potential Internet connection.
{"title":"An Attempt to Develop an IOT Based Vehicle Security System","authors":"Debajyoti Mukhopadhyay, Megha Gupta, Tahesin Attar, Prajakta S. Chavan, Vidhi S. Patel","doi":"10.1109/ISES.2018.00050","DOIUrl":"https://doi.org/10.1109/ISES.2018.00050","url":null,"abstract":"As the amount of urban vehicle grows rapidly, vehicle theft has become a shared concern for all citizens. Security and safety have always become a necessity for urban population. However, present anti-theft systems lack the tracking and monitoring function. Internet of things(IOT) has been governing the electronics era with cloud services dominating the ever-increasing electronics product segment. Thus, there is a need to develop a system for providing security to the vehicle from problems like theft and towing using IOT for security of automobiles and passengers. Our system proposes a novel security system based on wireless communication and a lowcost Bluetooth module. This paper illustrates a model in which the GSM is used for sending messages. the user can control the engine/ignition and turn it off if needed. The system also employs a password through keypad (with maximum 3 chances) which controls the opening of a safety locker door as well as wearing of a seat belt. If there is a window intruder, the IR module/sensor detects the intruder, or any obstacle and it sends a signal to the micro controller. The controller is connected to a Bluetooth module and to an alarm system. The System transmits an alert signal to the dashboard (which is nothing but a mobile handset) which sends an alert signal to the user's mobile phone. The prototype also provides a solution to the problem like Towing. Thus, the system uses Bluetooth module and controller to control the security system from the user's mobile phone by means of any device with a potential Internet connection.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121918421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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