A high speed and high resolution VLSI Winner-take-all circuit for neural networks and fuzzy systems

Abstract

The design and simulation of a novel CMOS voltage mode WTA (Winner-take-all) circuit is described. The circuit employs additional inhibitory and local excitatory feedback based on a common voltage computation and this improves both speed and precision drastically. As a result, a single stage cell provides better resolution in comparison to previous works where cascading of multiple stages is necessary to improve resolution. This makes the circuit suitable for systems where silicon area and power consumption are constraints. Moreover, the feedback arrangement ensures a single winner. Simulations in Cadence show that a single cell can resolve voltage differences as small as 0.5 mV in around 30ns with 1 pF load capacitance. Detailed simulation results along with appropriate mathematical relations have been provided. This circuit is a fundamental building block in the competitive layer of self organizing neural networks, non linear filters, fuzzy and neuromorphic systems.