Comparative analysis of 8 bit Carry Skip Adder using CMOS and PTL techniques with conventional MOSFET at 32 nanometer regime

P. P. Patil, A. A. Hatkar
{"title":"Comparative analysis of 8 bit Carry Skip Adder using CMOS and PTL techniques with conventional MOSFET at 32 nanometer regime","authors":"P. P. Patil, A. A. Hatkar","doi":"10.1109/ICPEICES.2016.7853414","DOIUrl":null,"url":null,"abstract":"The Carry Skip Adder (CSKA) is identified by a better efficiency in the trade off between operating speed and power dissipation, as it has a very low power-delay product, near to that of a carry-look ahead adder (CLA). A CSKA consists of blocks of full adder combined together, whose schematic (i.e., combination of full adders per block) mainly affects the overall operating speed of carry skip adder. These FA blocks are interconnected through 2∶1 multiplexers. Worst case delay can be reduced with different techniques which has been proposed for full adders, this paper provides an optimization technique only for the case of constant block size to improve the speed performance. The addition operations will result in sum value and carry value. In general, addition is a process which involves two numbers which are added and carry will be generated. The addition operations will result in sum value and carry value. In this paper, the performance parameters of delay, average power, PDP and EDP are compared at different technology node.","PeriodicalId":305942,"journal":{"name":"2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPEICES.2016.7853414","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

The Carry Skip Adder (CSKA) is identified by a better efficiency in the trade off between operating speed and power dissipation, as it has a very low power-delay product, near to that of a carry-look ahead adder (CLA). A CSKA consists of blocks of full adder combined together, whose schematic (i.e., combination of full adders per block) mainly affects the overall operating speed of carry skip adder. These FA blocks are interconnected through 2∶1 multiplexers. Worst case delay can be reduced with different techniques which has been proposed for full adders, this paper provides an optimization technique only for the case of constant block size to improve the speed performance. The addition operations will result in sum value and carry value. In general, addition is a process which involves two numbers which are added and carry will be generated. The addition operations will result in sum value and carry value. In this paper, the performance parameters of delay, average power, PDP and EDP are compared at different technology node.
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采用CMOS和PTL技术的8位进位跳加法器与传统MOSFET的32纳米制程比较分析
进位跳加法器(CSKA)在运行速度和功耗之间的权衡中具有更好的效率,因为它具有非常低的功率延迟产品,接近进位前置加法器(CLA)。CSKA由多个全加法器块组合而成,其原理图(即每个块的全加法器组合)主要影响进位跳加器的整体运行速度。这些FA模块通过2∶1多路复用器相互连接。对于全加法器,可以采用不同的方法来减少最坏情况下的延迟,本文只针对块大小不变的情况提出了一种优化方法,以提高速度性能。加法运算将产生和值和进位值。一般来说,加法是一个涉及两个数字相加并产生进位的过程。加法运算将产生和值和进位值。本文对不同技术节点下的时延、平均功率、PDP和EDP等性能参数进行了比较。
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