Comparative analysis of 8 bit Carry Skip Adder using CMOS and PTL techniques with conventional MOSFET at 32 nanometer regime

P. P. Patil, A. A. Hatkar
{"title":"Comparative analysis of 8 bit Carry Skip Adder using CMOS and PTL techniques with conventional MOSFET at 32 nanometer regime","authors":"P. P. Patil, A. A. Hatkar","doi":"10.1109/ICPEICES.2016.7853414","DOIUrl":null,"url":null,"abstract":"The Carry Skip Adder (CSKA) is identified by a better efficiency in the trade off between operating speed and power dissipation, as it has a very low power-delay product, near to that of a carry-look ahead adder (CLA). A CSKA consists of blocks of full adder combined together, whose schematic (i.e., combination of full adders per block) mainly affects the overall operating speed of carry skip adder. These FA blocks are interconnected through 2∶1 multiplexers. Worst case delay can be reduced with different techniques which has been proposed for full adders, this paper provides an optimization technique only for the case of constant block size to improve the speed performance. The addition operations will result in sum value and carry value. In general, addition is a process which involves two numbers which are added and carry will be generated. The addition operations will result in sum value and carry value. In this paper, the performance parameters of delay, average power, PDP and EDP are compared at different technology node.","PeriodicalId":305942,"journal":{"name":"2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPEICES.2016.7853414","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

The Carry Skip Adder (CSKA) is identified by a better efficiency in the trade off between operating speed and power dissipation, as it has a very low power-delay product, near to that of a carry-look ahead adder (CLA). A CSKA consists of blocks of full adder combined together, whose schematic (i.e., combination of full adders per block) mainly affects the overall operating speed of carry skip adder. These FA blocks are interconnected through 2∶1 multiplexers. Worst case delay can be reduced with different techniques which has been proposed for full adders, this paper provides an optimization technique only for the case of constant block size to improve the speed performance. The addition operations will result in sum value and carry value. In general, addition is a process which involves two numbers which are added and carry will be generated. The addition operations will result in sum value and carry value. In this paper, the performance parameters of delay, average power, PDP and EDP are compared at different technology node.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
采用CMOS和PTL技术的8位进位跳加法器与传统MOSFET的32纳米制程比较分析
进位跳加法器(CSKA)在运行速度和功耗之间的权衡中具有更好的效率,因为它具有非常低的功率延迟产品,接近进位前置加法器(CLA)。CSKA由多个全加法器块组合而成,其原理图(即每个块的全加法器组合)主要影响进位跳加器的整体运行速度。这些FA模块通过2∶1多路复用器相互连接。对于全加法器,可以采用不同的方法来减少最坏情况下的延迟,本文只针对块大小不变的情况提出了一种优化方法,以提高速度性能。加法运算将产生和值和进位值。一般来说,加法是一个涉及两个数字相加并产生进位的过程。加法运算将产生和值和进位值。本文对不同技术节点下的时延、平均功率、PDP和EDP等性能参数进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Renewable energy systems for generating electric power: A review A novel design of circular fractal antenna using inset line feed for multiband applications Integrated control of active front steer angle and direct yaw moment using Second Order Sliding Mode technique Voltage differencing buffered amplifier based quadrature oscillator Identification of higher order critically damped systems using relay feedback test
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1