A hardware algorithm for integer division

N. Takagi, Shunsuke Kadowaki, K. Takagi
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引用次数: 31

Abstract

A hardware algorithm for integer division is proposed. It is based on the digit-recurrence, non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit representation. The algorithm does not require normalization of the divisor, and hence, does not require area-consuming leading one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, where pipelining is possible for increasing the throughput. Sequential implementation yields a compact divider.
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整数除法的硬件算法
提出了一种整数除法的硬件算法。它基于数字递归、非还原除法算法。快速计算是通过使用基数2的符号数表示来实现的。该算法不需要规格化除数,因此,不需要消耗面积的前导1(或零)检测,也不需要变量量的移位。该算法的组合(展开)实现产生了一个规则结构化的数组分配器,其中流水线可以提高吞吐量。顺序实现产生一个紧凑的除法器。
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