Design of asynchronous circuit primitives using MOS current-mode logic (MCML)

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI:10.1109/ICM.2004.1434236

T. W. Kwan, M. Shams

引用次数: 3

Abstract

This paper introduces and compares two topologies for the C-element in MCML and two topologies for double-edge-triggered flip-flop in MCML. Based on the simulation results, an asynchronous MCML C-element dissipates four times less power than conventional static CMOS C-element at the same throughout of 1.9 GHz. Also, MCML double-edge-triggered flip-flop runs up to three times faster than the conventional static CMOS counterpart at the same power level. All the circuits are implemented in a standard 0.18 /spl mu/m CMOS technology.

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基于MOS电流模逻辑(MCML)的异步电路原语设计

本文介绍并比较了MCML中c元的两种拓扑结构和MCML中双边触发触发器的两种拓扑结构。仿真结果表明，在1.9 GHz的相同通频下，异步MCML C-element的功耗比传统静态CMOS C-element低4倍。此外，在相同功率水平下，MCML双边触发触发器的运行速度比传统静态CMOS触发器快三倍。所有电路都采用标准的0.18 /spl mu/m CMOS技术实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.

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