Classification and performance evaluation of instruction buffering techniques

Abstract

The speed disparity between processor and memory subsystenis has been bridged in many existing large- scale scientific computers and microproc.essors with the help of instruction burners or instruction caches. In this pa.per we 'classify t.hese bulrers into traditional in- struction buffers, conventional inst,ruct.ion caches and prefetch queues, det.ail their prominent. features, and evaluat.e.the percormanre of buffers in srveral cxisting -systems, using trace driven siinulat,ion. We compare ihse srhemes wit,ti a recentl) pro1iose"d queue-based in- sihction cache nieniory. An implementation indrprn- dent. perforrnaiice metric is proposed for thi. various or- ganizations and used for the evaluat.ions. M'r analyze the simulation results and discuss the eIfec.1 of various paralneters RIIC~ as prefetch threshold, bus width and buffer size on performance.