A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS

2011 IEEE 20th Symposium on Computer Arithmetic Pub Date : 2011-07-25 DOI:10.1109/ARITH.2011.20

T. Anderson, Duc Bui, S. Moharil, Soujanya Narnur, Mujibur Rahman, A. Lell, Eric Biscondi, A. Shrivastava, P. Dent, Mingjian Yan, Hasan Mahmood

引用次数: 9

Abstract

A next generation VLIW DSP Central Processing Unit (CPU) which has an integrated fixed point and floating point Instruction Set Architecture (ISA) is presented. It is designed to meet a 1.5 GHz core clock frequency in a 40nm process with aggressive area and power goals. In this paper, the benchmarking process and benefits of newly defined instructions such as complex matrix multiply is explained. Also, the CPU data path is described in detail, highlighting several novel micro-architecture features. Finally, our design methodology as well as verification methodology to ensure functional correctness utilizing formal equivalent verification is described.

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在40纳米CMOS中集成浮点和定点指令的1.5 Ghz VLIW DSP CPU

提出了一种集成定点和浮点指令集架构的新一代VLIW DSP中央处理器(CPU)。它的设计是为了满足在40nm工艺中的1.5 GHz核心时钟频率，具有侵略性的面积和功耗目标。本文阐述了新定义的复矩阵乘法等指令的基准测试过程和优点。此外，还详细描述了CPU数据路径，重点介绍了几个新的微体系结构特性。最后，描述了我们的设计方法以及使用形式等效验证来确保功能正确性的验证方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 IEEE 20th Symposium on Computer Arithmetic

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