A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic
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引用次数: 3
Abstract
A high-speed radix-64 parallel multiplier using novel reduced delay partial product generator is proposed. The use of radix-64 Booth encoder and selector for partial product generation by Sang-Hoon (Sang-Hoon Lee et al., 2002) reduces the number of partial product rows by six fold. The Booth selector selects one among X, 2X, 3X, 4X, 8X, 16X, 24X and 32X where X is the multiplicand. Before selection 3X computation must be completed which accounts for maximum delay because of carry propagation or carry look ahead addition of X and 2X. In this work this fundamental coefficient is generated as 4X-X using redundant binary (RB) arithmetic. This leads to zero delay for 3X computation as well as simplifies the partial product rows accumulation. This novel method of partial product generation decreases delay by 24% in comparison to last high-speed reported parallel multiplier (Sang-Hoon Lee et al., 2002) using radix-64 Booth encoding.
提出了一种基于新型减延迟部分积发生器的高速64根并行乘法器。Sang-Hoon (Sang-Hoon Lee et al., 2002)使用radix-64 Booth编码器和选择器生成部分产品,将部分产品行数减少了六倍。展台选择器从X、2X、3X、4X、8X、16X、24X、32X中选择一个,其中X为乘数。在选择之前必须完成3X计算,这是由于X和2X的进位传播或进位前瞻相加造成的最大延迟。在这项工作中,这个基本系数是用冗余二进制(RB)算法生成的4X-X。这使得3X计算的延迟为零,并简化了部分乘积行累积。这种新颖的部分积生成方法与上一个高速并行乘法器(Sang-Hoon Lee et al., 2002)使用基数64 Booth编码相比,延迟减少了24%。