{"title":"Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors","authors":"Ing-Jer Huang, Yi-Ju Ke, Shih-Jung Pao","doi":"10.1109/MCSoC57363.2022.00052","DOIUrl":null,"url":null,"abstract":"This paper presents a highly effective hybrid control flow error (CFE) detection and recovery mechanism for fault-tolerant instruction set processors. The mechanism consists of two innovations: critical signature assertion (CSA) and on-the-fly recovery (OTFR). The proposed mechanism is experimented with a commercial 32-bit microcontroller core, Andes N801s. Compared with related work, our approach achieves up to 75% and 221% lower in memory size and performance overheads respectively, and reduces the error correction latency by up to 54%, at the reasonable costs of 3470 gates (+19%) and 967uW (+17%) power and merely 0.3% sacrifice in fault coverage.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCSoC57363.2022.00052","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a highly effective hybrid control flow error (CFE) detection and recovery mechanism for fault-tolerant instruction set processors. The mechanism consists of two innovations: critical signature assertion (CSA) and on-the-fly recovery (OTFR). The proposed mechanism is experimented with a commercial 32-bit microcontroller core, Andes N801s. Compared with related work, our approach achieves up to 75% and 221% lower in memory size and performance overheads respectively, and reduces the error correction latency by up to 54%, at the reasonable costs of 3470 gates (+19%) and 967uW (+17%) power and merely 0.3% sacrifice in fault coverage.
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