Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00046
Cyril Elorm Kodjo Agbewali-Koku, Md.Atiqur Rahman, Mohamed Hamada, Mohammad Ameer Ali, Lutfun Nahar Oysharja, Md. Tazmim Hossain
The mode of education has changed over the past few years from the conventional method of in-person classes to the usage of online platforms to facilitate teaching and learning. These platforms popularly, known as online learning systems, have gradually become an integral part of education. These online platforms have been designed using various Artificial intelligence frameworks and techniques to enhance their functionality and personalize them for their users. Machine learning is one of the major fields of AI that has been used in most of these online platforms. Popular machine learning techniques such as deep learning, natural language processing, reinforcement learning, and others are being actively used and studied to further improve them for use. In this study, the focus will be on content analysis of different studies aimed at disclosing machine learning techniques that have been applied in the online learning sector and exploring the potential research trends and challenges of integrating machine learning techniques in online learning. The study will focus on published papers from the year 2015 to 2021, classifying them based on the research question.
{"title":"A systematic review of machine learning techniques in online learning platforms","authors":"Cyril Elorm Kodjo Agbewali-Koku, Md.Atiqur Rahman, Mohamed Hamada, Mohammad Ameer Ali, Lutfun Nahar Oysharja, Md. Tazmim Hossain","doi":"10.1109/MCSoC57363.2022.00046","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00046","url":null,"abstract":"The mode of education has changed over the past few years from the conventional method of in-person classes to the usage of online platforms to facilitate teaching and learning. These platforms popularly, known as online learning systems, have gradually become an integral part of education. These online platforms have been designed using various Artificial intelligence frameworks and techniques to enhance their functionality and personalize them for their users. Machine learning is one of the major fields of AI that has been used in most of these online platforms. Popular machine learning techniques such as deep learning, natural language processing, reinforcement learning, and others are being actively used and studied to further improve them for use. In this study, the focus will be on content analysis of different studies aimed at disclosing machine learning techniques that have been applied in the online learning sector and exploring the potential research trends and challenges of integrating machine learning techniques in online learning. The study will focus on published papers from the year 2015 to 2021, classifying them based on the research question.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125434251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00049
Hida Masataka, Y. Watanobe
There are barriers between general public people and professionals or computers. This barrier can also be seen in an educational situation. The purpose of this study is to break the barriers and reduce the learning cost, misunderstandings, and conflicts among people, computers, and knowledge in studying. This study attempted to find a way to provide information to the general public by using the software. In this paper, “general people” stands for students or people learning new skills and professional knowledge or people who have no knowledge of the field. As a case study, this study will create a user-friendly SQL system for non-experts. Approaches are mainly presented from the UI design of software and the usage of professional terms and words. The concept of Human-Driven Design(HDD) is also used. This paper researches the balance of interaction between humans and technology when using software. Based on HDD, this study also considers the sustainability of the database field and creates an opportunity to consider the reasons why the wall between experts and non-experts appears.
{"title":"Making Software Based on Human-Driven Design Case Study: SQL for non-experts","authors":"Hida Masataka, Y. Watanobe","doi":"10.1109/MCSoC57363.2022.00049","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00049","url":null,"abstract":"There are barriers between general public people and professionals or computers. This barrier can also be seen in an educational situation. The purpose of this study is to break the barriers and reduce the learning cost, misunderstandings, and conflicts among people, computers, and knowledge in studying. This study attempted to find a way to provide information to the general public by using the software. In this paper, “general people” stands for students or people learning new skills and professional knowledge or people who have no knowledge of the field. As a case study, this study will create a user-friendly SQL system for non-experts. Approaches are mainly presented from the UI design of software and the usage of professional terms and words. The concept of Human-Driven Design(HDD) is also used. This paper researches the balance of interaction between humans and technology when using software. Based on HDD, this study also considers the sustainability of the database field and creates an opportunity to consider the reasons why the wall between experts and non-experts appears.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122508626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00063
Yuqing Zhou, Naoya Niwa, H. Amano
NoC(Network-on-Chip)s is an essential component of recent multi-core systems. When the number of wires available on a chip is limited, it is sometimes congested and increased la-tency can degrade the parallel application performance. The selective data compression has been proposed to mitigate such network congestion by compressing and decompressing packets based on the packet length and traffic situation. However, since the algorithm does not care the location of nodes, the compression and decompression are performed even when the packet is transferred between neighboring nodes. This paper proposes a distance aware (DA) compression mechanism to select whether the packet should be compressed by the distance to the destination. The packets to the nodes whose distance is larger than threshold level are compressed with a run-length loss-less compression at the sender's network interface and de-compressed at the receiver's network interface. Cycle level network simulation results show that the selective compression method achieves up to 45% bandwidth improve-ment with 1.26 times increase of the latency.
{"title":"Distance Aware Compression for Low Latency High Bandwidth Interconnection Network","authors":"Yuqing Zhou, Naoya Niwa, H. Amano","doi":"10.1109/MCSoC57363.2022.00063","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00063","url":null,"abstract":"NoC(Network-on-Chip)s is an essential component of recent multi-core systems. When the number of wires available on a chip is limited, it is sometimes congested and increased la-tency can degrade the parallel application performance. The selective data compression has been proposed to mitigate such network congestion by compressing and decompressing packets based on the packet length and traffic situation. However, since the algorithm does not care the location of nodes, the compression and decompression are performed even when the packet is transferred between neighboring nodes. This paper proposes a distance aware (DA) compression mechanism to select whether the packet should be compressed by the distance to the destination. The packets to the nodes whose distance is larger than threshold level are compressed with a run-length loss-less compression at the sender's network interface and de-compressed at the receiver's network interface. Cycle level network simulation results show that the selective compression method achieves up to 45% bandwidth improve-ment with 1.26 times increase of the latency.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124662047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00018
D. Suzuki, T. Hanyu
A nonvolatile (NV) field-programmable gate array (FPGA) is quite attractive hardware platform for an internet of things (IoT) device in terms of reconfigurability and ultra-low-power standby power consumption. Moreover, the use of NV logic-in-memory (LIM) circuitry makes it possible to im-prove both area efficiency and energy efficiency. In this paper, some related topics about NV-FPGA, NV-LIM circuitry, and its application to the edge-AI accelerator are presented and its effectiveness is demonstrated.
{"title":"A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator","authors":"D. Suzuki, T. Hanyu","doi":"10.1109/MCSoC57363.2022.00018","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00018","url":null,"abstract":"A nonvolatile (NV) field-programmable gate array (FPGA) is quite attractive hardware platform for an internet of things (IoT) device in terms of reconfigurability and ultra-low-power standby power consumption. Moreover, the use of NV logic-in-memory (LIM) circuitry makes it possible to im-prove both area efficiency and energy efficiency. In this paper, some related topics about NV-FPGA, NV-LIM circuitry, and its application to the edge-AI accelerator are presented and its effectiveness is demonstrated.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129444760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00043
R. SoujanyaS., M. Rao
Deployment of deep neural network (DNN) infer-ence on platforms like field programmable gate array (FPGA) for acceleration can be challenging because of the limited resource availability and a large number of floating-point matrix operations involved. Therefore, in this work a hardware efficient algorithm called Integer-Net which is based on approximate floating-point operations is studied for edge DNN inference deployment. This algorithm uses integerized floating-point arithmetic with a scalar correction for the matrix operations. Electroencephalo-gram (EEG) signal based automatic high-speed epileptic seizure detection using Integer-Net convolutional neural network (CNN) was hardware-implemented on Zynq-7000 SoC to characterize performance efficiency and hardware resources utilized against the full precision model. Implementation was benefited by the accelerated outputs, leveraged the optimum on-board resources, and at the same time with the help of configurable integer bit-width, facilitated keeping the accuracy close to the original model. This is the first time, Integer-Net based designs and their novel hybrid versions were employed and investigated for the hardware acceleration of a CNN network for seizure detection on FPG A. A latency acceleration of 5.65x with the on-chip memory usage reduction factor of 5.99x was achieved by the optimized hybrid integerized CNN model.
{"title":"Hardware characterization of Integer-Net based seizure detection models on FPGA","authors":"R. SoujanyaS., M. Rao","doi":"10.1109/MCSoC57363.2022.00043","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00043","url":null,"abstract":"Deployment of deep neural network (DNN) infer-ence on platforms like field programmable gate array (FPGA) for acceleration can be challenging because of the limited resource availability and a large number of floating-point matrix operations involved. Therefore, in this work a hardware efficient algorithm called Integer-Net which is based on approximate floating-point operations is studied for edge DNN inference deployment. This algorithm uses integerized floating-point arithmetic with a scalar correction for the matrix operations. Electroencephalo-gram (EEG) signal based automatic high-speed epileptic seizure detection using Integer-Net convolutional neural network (CNN) was hardware-implemented on Zynq-7000 SoC to characterize performance efficiency and hardware resources utilized against the full precision model. Implementation was benefited by the accelerated outputs, leveraged the optimum on-board resources, and at the same time with the help of configurable integer bit-width, facilitated keeping the accuracy close to the original model. This is the first time, Integer-Net based designs and their novel hybrid versions were employed and investigated for the hardware acceleration of a CNN network for seizure detection on FPG A. A latency acceleration of 5.65x with the on-chip memory usage reduction factor of 5.99x was achieved by the optimized hybrid integerized CNN model.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127988977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00023
Riadh Ben Abdelhamid, Y. Yamaguchi
For over a half-century, computer architects have explored micro-architecture, instruction set architecture, and system architecture to offer a significant performance boost out of a computing chip. In the micro-architecture, multi-processing and multi-threading arose as fusing highly parallel processing and the growth of semiconductor manufacturing technology. It has caused a paradigm shift in computing chips and led to the many-core processor age, such as NVIDIA GPUs, Movidius Myriad, PEZY ZettaScaler, and the project Eyeriss based on a reconfigurable accelerator. Wherein packed SIMD (Single Instruction Multiple Data) vectorizations attract attention, especially from ML (machine learning) applications. It can achieve more energy-efficient computing by reducing computing precision, which is enough for ML applications to obtain the results with low-accuracy calculations. In other words, accuracy-flexible computing needs to allow splitting off one N-bit ALU (Arithmetic Logic Unit) or one N-bit FPU (Floating-Point Unit) into multiple $M$-bit units. For example, a double-precision (64-bit operands width) FPU can be split into two single-precision (32-bit operands width) FPUs, or four half-precision (16-bit operands width) FPUs. Consequently, instead of executing one original operation, a packed SIMD vectorization simultaneously enables executing two or four reduced-precision operations. This article proposes a packed SIMD vectorization approach, which considers the Dynamically Reprogrammable Architecture of Gather-scatter Overlay Nodes-Compact Buffering (DRAGON2-CB) many-core overlay architecture. In particular, this article presents a thorough comparative study between packed SIMD using dual single-precision and quad half-precision FPU-only many-core overlays compared to the non-vectorized double-precision version.
{"title":"Packed SIMD Vectorization of the DRAGON2-CB","authors":"Riadh Ben Abdelhamid, Y. Yamaguchi","doi":"10.1109/MCSoC57363.2022.00023","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00023","url":null,"abstract":"For over a half-century, computer architects have explored micro-architecture, instruction set architecture, and system architecture to offer a significant performance boost out of a computing chip. In the micro-architecture, multi-processing and multi-threading arose as fusing highly parallel processing and the growth of semiconductor manufacturing technology. It has caused a paradigm shift in computing chips and led to the many-core processor age, such as NVIDIA GPUs, Movidius Myriad, PEZY ZettaScaler, and the project Eyeriss based on a reconfigurable accelerator. Wherein packed SIMD (Single Instruction Multiple Data) vectorizations attract attention, especially from ML (machine learning) applications. It can achieve more energy-efficient computing by reducing computing precision, which is enough for ML applications to obtain the results with low-accuracy calculations. In other words, accuracy-flexible computing needs to allow splitting off one N-bit ALU (Arithmetic Logic Unit) or one N-bit FPU (Floating-Point Unit) into multiple $M$-bit units. For example, a double-precision (64-bit operands width) FPU can be split into two single-precision (32-bit operands width) FPUs, or four half-precision (16-bit operands width) FPUs. Consequently, instead of executing one original operation, a packed SIMD vectorization simultaneously enables executing two or four reduced-precision operations. This article proposes a packed SIMD vectorization approach, which considers the Dynamically Reprogrammable Architecture of Gather-scatter Overlay Nodes-Compact Buffering (DRAGON2-CB) many-core overlay architecture. In particular, this article presents a thorough comparative study between packed SIMD using dual single-precision and quad half-precision FPU-only many-core overlays compared to the non-vectorized double-precision version.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130181582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00056
Ashish Reddy Bommana, Srinivas Boppu
In this era of widespread embedded computing, energy efficiency has become the new performance criterion; as a result, accelerator-rich multi-processor system-on-chips are widely utilized in embedded computing hardware. Due to abun-dant and inexpensive computational capacity, computationally intensive machine learning applications have gained a lot of traction and are currently being used in a wide range of application domains. Furthermore, there is an increasing trend toward developing hardware accelerators for machine learning applications for embedded edge devices where performance and energy efficiency are critical. Although floating-point operations are frequently used for accuracy in these hardware accelerators, reduced width floating point formats are also used to reduce hardware complexity and thus power consumption while pre-serving accuracy. Mixed-precision DNN, vectorization techniques, and any-precision DNN concepts have also proven to boost performance, energy efficiency, and memory bandwidth. In this paper, we propose the design of a vectorized floating-point adder/subtractor that can handle arbitrary length floating-point formats with varying exponent and mantissa widths. The whole idea of this paper is to bring flexibility to each layer in a DNN model for arithmetic operations; depending on the requirement of computation of each layer, exponent width and the floating-point format are chosen dynamically. In comparison to existing designs in the literature, the proposed design is $1.69times$ area and $1.61times$ power-efficient, and it supports true vectorization with no restrictions on exponent and mantissa widths.
{"title":"A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization","authors":"Ashish Reddy Bommana, Srinivas Boppu","doi":"10.1109/MCSoC57363.2022.00056","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00056","url":null,"abstract":"In this era of widespread embedded computing, energy efficiency has become the new performance criterion; as a result, accelerator-rich multi-processor system-on-chips are widely utilized in embedded computing hardware. Due to abun-dant and inexpensive computational capacity, computationally intensive machine learning applications have gained a lot of traction and are currently being used in a wide range of application domains. Furthermore, there is an increasing trend toward developing hardware accelerators for machine learning applications for embedded edge devices where performance and energy efficiency are critical. Although floating-point operations are frequently used for accuracy in these hardware accelerators, reduced width floating point formats are also used to reduce hardware complexity and thus power consumption while pre-serving accuracy. Mixed-precision DNN, vectorization techniques, and any-precision DNN concepts have also proven to boost performance, energy efficiency, and memory bandwidth. In this paper, we propose the design of a vectorized floating-point adder/subtractor that can handle arbitrary length floating-point formats with varying exponent and mantissa widths. The whole idea of this paper is to bring flexibility to each layer in a DNN model for arithmetic operations; depending on the requirement of computation of each layer, exponent width and the floating-point format are chosen dynamically. In comparison to existing designs in the literature, the proposed design is $1.69times$ area and $1.61times$ power-efficient, and it supports true vectorization with no restrictions on exponent and mantissa widths.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124824833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00054
R. Cowan, T. Davis, B. Kundu, J. Rolston, Elliot H. Smith
Impulsive choice is a facet of impulsivity that may lead to one to choose smaller, more immediate rewards over larger, delayed rewards. Impulsive choice is a kind of maladaptive decision making that is a fundamental element of relapse in substance use disorder. Despite its essential role in relapse, there is currently little understanding of the neural basis of impulsive choices. Better understanding of the neural correlates of impulsivity could lead to improved diagnosis and treatment of psychiatric disorders in which impulsive choice plays a role. In this work, we examined impulsive choice behavior in humans undergoing intracranial seizure monitoring by fitting temporal difference learning models to behavior and broadband high frequency (70–150 Hz) local field potentials. We found neural and behavioral differences between more and less impulsive choosers, informing the neural underpinnings of impulsive choices and describing a biomarker for reward expectation and surprise in the human brain.
{"title":"Neuronal population biomarkers of temporal difference learning in human impulsive choices","authors":"R. Cowan, T. Davis, B. Kundu, J. Rolston, Elliot H. Smith","doi":"10.1109/MCSoC57363.2022.00054","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00054","url":null,"abstract":"Impulsive choice is a facet of impulsivity that may lead to one to choose smaller, more immediate rewards over larger, delayed rewards. Impulsive choice is a kind of maladaptive decision making that is a fundamental element of relapse in substance use disorder. Despite its essential role in relapse, there is currently little understanding of the neural basis of impulsive choices. Better understanding of the neural correlates of impulsivity could lead to improved diagnosis and treatment of psychiatric disorders in which impulsive choice plays a role. In this work, we examined impulsive choice behavior in humans undergoing intracranial seizure monitoring by fitting temporal difference learning models to behavior and broadband high frequency (70–150 Hz) local field potentials. We found neural and behavioral differences between more and less impulsive choosers, informing the neural underpinnings of impulsive choices and describing a biomarker for reward expectation and surprise in the human brain.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115624371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00055
N. A. Quadir, M. Hamdi, M. A. Awan, Bo Wang, A. Bermak
Passive radio-frequency identification (RFID) tags, when placed remotely or in harsh environments, will benefit the most if the communication distance between the tag and reader is vastly improved. The bistatic backscattering technique provides a solution to this problem by separating the carrier and backscattered signal in frequency, which helps mitigate interference. It also decouples the reader from carrier generation by having a separate radio-frequency (RF) emitter and further improves the signal strength by reducing round trip path loss. A dual-band on-chip bistatic backscattering circuit design for passive RFID tags is presented in this paper using a 180 nm CMOS process dissipating 35 $mu mathrm{W}$ of power. Post layout simulation results provide a communicable distance of 170 m between the tag and reader at 868 MHz and 60 m at 2.4 GHz when the tag is kept 5 m away from the RF emitter.
{"title":"Design and Analysis of A Dual-Band Bistatic Backscatter Circuit for Passive RFID Tags","authors":"N. A. Quadir, M. Hamdi, M. A. Awan, Bo Wang, A. Bermak","doi":"10.1109/MCSoC57363.2022.00055","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00055","url":null,"abstract":"Passive radio-frequency identification (RFID) tags, when placed remotely or in harsh environments, will benefit the most if the communication distance between the tag and reader is vastly improved. The bistatic backscattering technique provides a solution to this problem by separating the carrier and backscattered signal in frequency, which helps mitigate interference. It also decouples the reader from carrier generation by having a separate radio-frequency (RF) emitter and further improves the signal strength by reducing round trip path loss. A dual-band on-chip bistatic backscattering circuit design for passive RFID tags is presented in this paper using a 180 nm CMOS process dissipating 35 $mu mathrm{W}$ of power. Post layout simulation results provide a communicable distance of 170 m between the tag and reader at 868 MHz and 60 m at 2.4 GHz when the tag is kept 5 m away from the RF emitter.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132654760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00041
Shouhei Yamanashi, H. Yashiro, T. Katagiri, Toru Nagai, S. Ohshima
Mixed-precision computation mainly focuses on shortening the execution time, at the expense of accuracy. To achieve speedups for numerical calculation using mixed-precision computation, it is necessary to tune software performance with respect to not only execution speed but also computation accuracy and power consumption. This increases the overall cost of tuning. Autotuning (AT) is one of the candidates among several technologies available for reducing the cost associated with tuning the software performance. In this study, we propose a method for AT to obtain speedups with respect to computation accuracy and power consumption. The proposed AT method uses an AT language that changes computation accuracy of the original code to mixed-precision by combining double and single precisions. Performance evaluation was carried out by using the Fujitsu PRIMEHPC FX1000, which is a “Fugaku” type supercomputer installed at the Information Technology Center, Nagoya University. The proposed method achieved a 1.5x reduction in execution time and energy consumption while retaining reasonable accuracy degradation from the original code of a global cloud resolving model.
{"title":"Autotuning Power Consumption and Computation Accuracy using ppOpen-AT","authors":"Shouhei Yamanashi, H. Yashiro, T. Katagiri, Toru Nagai, S. Ohshima","doi":"10.1109/MCSoC57363.2022.00041","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00041","url":null,"abstract":"Mixed-precision computation mainly focuses on shortening the execution time, at the expense of accuracy. To achieve speedups for numerical calculation using mixed-precision computation, it is necessary to tune software performance with respect to not only execution speed but also computation accuracy and power consumption. This increases the overall cost of tuning. Autotuning (AT) is one of the candidates among several technologies available for reducing the cost associated with tuning the software performance. In this study, we propose a method for AT to obtain speedups with respect to computation accuracy and power consumption. The proposed AT method uses an AT language that changes computation accuracy of the original code to mixed-precision by combining double and single precisions. Performance evaluation was carried out by using the Fujitsu PRIMEHPC FX1000, which is a “Fugaku” type supercomputer installed at the Information Technology Center, Nagoya University. The proposed method achieved a 1.5x reduction in execution time and energy consumption while retaining reasonable accuracy degradation from the original code of a global cloud resolving model.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133743264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：