H. Kleines, P. Wustner, M. Drochner, A. Ackens, M. Ramm, S. van Waasen
{"title":"Concentrator for the readout of the PANDA Micro Vertex Detector based on MicroTCA","authors":"H. Kleines, P. Wustner, M. Drochner, A. Ackens, M. Ramm, S. van Waasen","doi":"10.1109/RTC.2016.7543125","DOIUrl":null,"url":null,"abstract":"The Micro Vertex Detector (MVD) will be used as the central tracking detector in the PANDA (AntiProton Annihilation at Darmstadt) detector system which is under development for the future accelerator facility FAIR in Darmstadt, Germany. The design of the MVD is based on silicon strip detectors at the outer layer and on silicon pixel detectors at the inner layers. Data from the readout ASICs in the front end will be sent via GBT optical links to a multiplexing layer aggregating them to 10 Gbit/s optical uplinks to the Level-1 Trigger network. The multiplexing layer will be based on MTCA.4 using the HGF-AMC, a versatile MTCA.4 module developed by DESY in cooperation with KIT. In order to extend the multiplexing capabilities of the HGF-AMC, a Rear Transition Module (RTM) with 8 optical links has been designed.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE-NPSS Real Time Conference (RT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTC.2016.7543125","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The Micro Vertex Detector (MVD) will be used as the central tracking detector in the PANDA (AntiProton Annihilation at Darmstadt) detector system which is under development for the future accelerator facility FAIR in Darmstadt, Germany. The design of the MVD is based on silicon strip detectors at the outer layer and on silicon pixel detectors at the inner layers. Data from the readout ASICs in the front end will be sent via GBT optical links to a multiplexing layer aggregating them to 10 Gbit/s optical uplinks to the Level-1 Trigger network. The multiplexing layer will be based on MTCA.4 using the HGF-AMC, a versatile MTCA.4 module developed by DESY in cooperation with KIT. In order to extend the multiplexing capabilities of the HGF-AMC, a Rear Transition Module (RTM) with 8 optical links has been designed.