Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube Interconnects

Abstract

In the nanometer regime carbon nanotube has been a potential candidate in replacing the traditional copper based interconnects. The work in this paper analyzes the delay of multi-wall carbon nanotube (MWCNT) based interconnect systems at the system level by implementing a four-bit array multiplier using MWCNT based interconnects. The layout of the multiplier is drawn using MWCNT based interconnects and delay has been analyzed and compared with that of the traditional copper based interconnects. It has been observed that MWCNT based design has 3.4% less delay in the critical path as compared to the copper based design. The paper also describes a methodology of modeling and analyzing a system designed with MWCNT interconnects, using the conventional chip design flow and tools.