Due to its promising applications in domains like quantum computation or low-power design, synthesis of reversible circuits has become an intensely studied topic. However, many synthesis methods are limited by non-scalable function representations like truth tables. As an alternative, synthesis exploiting graph-based representations have been suggested. The underlying structure is a decision diagram (DD) that may vary regarding reduction methods, decomposition rules, or ordering restrictions. In this work, we review the progress of DD-based synthesis. It is shown that dedicated transformation rules can be applied to generate circuits for functions with a large number of inputs. We discuss the effect of different decomposition types or typical DD improvements like complement edges and re-ordering. Furthermore, we describe how DD-based synthesis can be exploited to transfer theoretical results known from decision diagrams into the domain of reversible circuits. Finally, further directions for future work are outlined.
{"title":"Synthesis of Reversible Circuits Using Decision Diagrams","authors":"R. Drechsler, R. Wille","doi":"10.1109/ISED.2012.37","DOIUrl":"https://doi.org/10.1109/ISED.2012.37","url":null,"abstract":"Due to its promising applications in domains like quantum computation or low-power design, synthesis of reversible circuits has become an intensely studied topic. However, many synthesis methods are limited by non-scalable function representations like truth tables. As an alternative, synthesis exploiting graph-based representations have been suggested. The underlying structure is a decision diagram (DD) that may vary regarding reduction methods, decomposition rules, or ordering restrictions. In this work, we review the progress of DD-based synthesis. It is shown that dedicated transformation rules can be applied to generate circuits for functions with a large number of inputs. We discuss the effect of different decomposition types or typical DD improvements like complement edges and re-ordering. Furthermore, we describe how DD-based synthesis can be exploited to transfer theoretical results known from decision diagrams into the domain of reversible circuits. Finally, further directions for future work are outlined.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122865596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sudip Roy, B. Bhattacharya, S. Ghoshal, K. Chakrabarty
Recently developed digital microfluidic biochips can implement biochemical laboratory assays (protocols) on a small size chip for automatic and reliable analysis of biochemical fluid samples. Dilution of a sample fluid is the basic step required in almost all bioassays. We propose a dilution engine for sample preparation that can produce multiple (a stream of) droplets of the target fluid with the same concentration level and present a scheduling scheme for mapping the dilution steps into the dilution engine. Our proposed architecture for dilution engine uses one ($1:1$) mix-split microfluidic module (mixer) and a constant number of storage units. Its performance is compared with another layout of only one mixer with no storage unit. Simulation results show that the proposed scheme can efficiently reuse the waste droplets of earlier steps and hence utilizes less amount of expensive biochemical fluids. Moreover, the scheme generates multiple target droplets with the same concentration level in less number of dilution steps (i.e., time) and at a relatively lower cost.
{"title":"Low-Cost Dilution Engine for Sample Preparation in Digital Microfluidic Biochips","authors":"Sudip Roy, B. Bhattacharya, S. Ghoshal, K. Chakrabarty","doi":"10.1109/ISED.2012.70","DOIUrl":"https://doi.org/10.1109/ISED.2012.70","url":null,"abstract":"Recently developed digital microfluidic biochips can implement biochemical laboratory assays (protocols) on a small size chip for automatic and reliable analysis of biochemical fluid samples. Dilution of a sample fluid is the basic step required in almost all bioassays. We propose a dilution engine for sample preparation that can produce multiple (a stream of) droplets of the target fluid with the same concentration level and present a scheduling scheme for mapping the dilution steps into the dilution engine. Our proposed architecture for dilution engine uses one ($1:1$) mix-split microfluidic module (mixer) and a constant number of storage units. Its performance is compared with another layout of only one mixer with no storage unit. Simulation results show that the proposed scheme can efficiently reuse the waste droplets of earlier steps and hence utilizes less amount of expensive biochemical fluids. Moreover, the scheme generates multiple target droplets with the same concentration level in less number of dilution steps (i.e., time) and at a relatively lower cost.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123496291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel design for the implementation of the 2M x 3P x 5Q point Discrete Fourier Transform (DFT) computation for Single Carrier-Frequency Division Multiple Access (SC-FDMA) systems as defined by the Long Term Evolution standard is proposed. The design is based on the Systolic Architecture. The decomposition of the DFT computation into factors of two, three, four and five is implemented by a recursive invocation of the Cooley-Tukey Algorithm, with the individual DFTs within each Cooley Tukey iteration implemented using the Winograd Fourier Transform Algorithm (WFTA). The proposed architecture is superior to the Intellectual Property (IP) cores proposed by Xilinx R in that the clock frequency requirements are reduced by a factor of up to 5.2 (approx), resulting in significant savings in the total power dissipation.
{"title":"Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term Evolution","authors":"C. V. Niras, Vinu Thomas","doi":"10.1109/ISED.2012.47","DOIUrl":"https://doi.org/10.1109/ISED.2012.47","url":null,"abstract":"A novel design for the implementation of the 2M x 3P x 5Q point Discrete Fourier Transform (DFT) computation for Single Carrier-Frequency Division Multiple Access (SC-FDMA) systems as defined by the Long Term Evolution standard is proposed. The design is based on the Systolic Architecture. The decomposition of the DFT computation into factors of two, three, four and five is implemented by a recursive invocation of the Cooley-Tukey Algorithm, with the individual DFTs within each Cooley Tukey iteration implemented using the Winograd Fourier Transform Algorithm (WFTA). The proposed architecture is superior to the Intellectual Property (IP) cores proposed by Xilinx R in that the clock frequency requirements are reduced by a factor of up to 5.2 (approx), resulting in significant savings in the total power dissipation.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114422905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
FIR filters are the most common DSP function implemented in FPGAs. Systolic designs represent an attractive architectural paradigm for efficient VLSI and FPGA implementation of computation-intensive digital signal processing applications supported by the features like simplicity, regularity, and modularity of structure. The core elements in any systolic FIR filters are adders, multipliers and delay elements. Adders are one of the critical elements in VLSI chips, therefore careful optimization is required. This paper presents the implementation of systolic FIR filter architecture in FPGA. The work focuses the design of new parallel prefix adder (PPA) with minimal depth algorithm and its performance is compared with the existing architectures in terms of delay and area. The necessities of the parallel prefix adder are primarily fast and secondarily efficient in terms of power consumption and chip area. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size. The proposed adder and the existing PPA is incorporated in the systolic FIR filter and its performances are observed. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, input arrival time, frequency are analyzed at 90 nm process technology using XILINX ISE12.1 SPARTAN3E. The simulation results reveal better delay and slice utilization for proposed PPA as compare to the existing adder schemes.
{"title":"Systolic FIR Filter Design with Various Parallel Prefix Adders in FPGA: Performance Analysis","authors":"R. Uma, Jebashini Ponnian","doi":"10.1109/ISED.2012.45","DOIUrl":"https://doi.org/10.1109/ISED.2012.45","url":null,"abstract":"FIR filters are the most common DSP function implemented in FPGAs. Systolic designs represent an attractive architectural paradigm for efficient VLSI and FPGA implementation of computation-intensive digital signal processing applications supported by the features like simplicity, regularity, and modularity of structure. The core elements in any systolic FIR filters are adders, multipliers and delay elements. Adders are one of the critical elements in VLSI chips, therefore careful optimization is required. This paper presents the implementation of systolic FIR filter architecture in FPGA. The work focuses the design of new parallel prefix adder (PPA) with minimal depth algorithm and its performance is compared with the existing architectures in terms of delay and area. The necessities of the parallel prefix adder are primarily fast and secondarily efficient in terms of power consumption and chip area. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size. The proposed adder and the existing PPA is incorporated in the systolic FIR filter and its performances are observed. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, input arrival time, frequency are analyzed at 90 nm process technology using XILINX ISE12.1 SPARTAN3E. The simulation results reveal better delay and slice utilization for proposed PPA as compare to the existing adder schemes.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121956855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the analysis of a soft switching boost converter for PV applications. The designed converter maintains Zero Voltage Switching (ZVS) turn on and turn off of the main switch and Zero Current Switching (ZCS) turn on and ZVS turn off of the auxiliary switch. Detailed operation, analysis and simulation results for the design have been presented. Switching and conduction losses across the switches and the diodes have also been calculated and analyzed. Some light has been thrown on the design of inductor for the practical implementation of the same. The Perturbation and Observation (P &O) method has been used in order to track the Maximum Power Point (MPP) from the PV panel. This soft switching technique can be used in telecom services where there is a necessity of high voltage with low DC power. The systems are modeled and simulated in PSIM 64 bit version 9.0 environment.
{"title":"An Improved Soft Switching DC-DC Converter for Low Power PV Applications","authors":"S. Bal, A. Anurag, B. Babu","doi":"10.1109/ISED.2012.34","DOIUrl":"https://doi.org/10.1109/ISED.2012.34","url":null,"abstract":"This paper presents the analysis of a soft switching boost converter for PV applications. The designed converter maintains Zero Voltage Switching (ZVS) turn on and turn off of the main switch and Zero Current Switching (ZCS) turn on and ZVS turn off of the auxiliary switch. Detailed operation, analysis and simulation results for the design have been presented. Switching and conduction losses across the switches and the diodes have also been calculated and analyzed. Some light has been thrown on the design of inductor for the practical implementation of the same. The Perturbation and Observation (P &O) method has been used in order to track the Maximum Power Point (MPP) from the PV panel. This soft switching technique can be used in telecom services where there is a necessity of high voltage with low DC power. The systems are modeled and simulated in PSIM 64 bit version 9.0 environment.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121723407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Banerjee, S. Datta, Pratyusha Das, A. Konar, D. Tibarewala, R. Janarthanan
Human computer interfacing technology has paved a new way in providing services to people with special needs (i.e., elderly, people with impairments, or people with disabilities). Research is going on to interface the movement based biosignals with machines. Electrooculogram is the signal produced due to eye ball movements and can be used to control mobility aids. Electrooculogram is the potential difference around the eyes due to movement of the eye balls in different directions. In this study an acquisition system for electrooculogram is designed to collect the desired signal with low noise and then signal processing is done for control application. The contribution of this paper lies in the development of two new strategies of electrooculographic signal based control of motors in real time.
{"title":"Electrooculogram Based Online Control Signal Generation for Wheelchair","authors":"A. Banerjee, S. Datta, Pratyusha Das, A. Konar, D. Tibarewala, R. Janarthanan","doi":"10.1109/ISED.2012.12","DOIUrl":"https://doi.org/10.1109/ISED.2012.12","url":null,"abstract":"Human computer interfacing technology has paved a new way in providing services to people with special needs (i.e., elderly, people with impairments, or people with disabilities). Research is going on to interface the movement based biosignals with machines. Electrooculogram is the signal produced due to eye ball movements and can be used to control mobility aids. Electrooculogram is the potential difference around the eyes due to movement of the eye balls in different directions. In this study an acquisition system for electrooculogram is designed to collect the desired signal with low noise and then signal processing is done for control application. The contribution of this paper lies in the development of two new strategies of electrooculographic signal based control of motors in real time.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130076341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Syed Ershad Ahmed, S. Abraham, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas
This paper presents a twin precision multiplier with modified 2-D bypass Logic. The multiplier can perform one 8-bit multiplication or two 4-bit multiplications. The multiplier structure is modified by adding a 2-dimensional modified bypassing logic resulting in reduction in dynamic power as well the delay. Simulation results indicate that with a marginal increase in area, the proposed twin precision multiplier achieves an improvement of 25.5% in delay and up to 29% reduction of power-delay product when compared to existing designs.
{"title":"A Modified Twin Precision Multiplier with 2D Bypassing Technique","authors":"Syed Ershad Ahmed, S. Abraham, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas","doi":"10.1109/ISED.2012.58","DOIUrl":"https://doi.org/10.1109/ISED.2012.58","url":null,"abstract":"This paper presents a twin precision multiplier with modified 2-D bypass Logic. The multiplier can perform one 8-bit multiplication or two 4-bit multiplications. The multiplier structure is modified by adding a 2-dimensional modified bypassing logic resulting in reduction in dynamic power as well the delay. Simulation results indicate that with a marginal increase in area, the proposed twin precision multiplier achieves an improvement of 25.5% in delay and up to 29% reduction of power-delay product when compared to existing designs.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"37 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133008111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Suman, B. V. S. P. Kumar, M. S. Kumar, B. Babu, K. Subhashini
In this paper, modeling, analysis and design of synchronous buck converter for low power photo-voltaic (PV) energy system is presented. For analyzing the performance such converter, first we studied the characteristics of PV array under different values of irradiance and temperature. Then the exquisite design of synchronous buck converter with the application of State Space Averaging to implement precise control design for the converter is presented. The synchronous buck converter thus designed is used for portable appliances such as mobiles, laptops, iPod's laptops, etc. In addition to that, closed loop control of synchronous buck converter is studied in order to meet the dynamic energy requirement of load especially during variation of source i.e. variation of solar irradiation and temperature. Further, the efficiency of synchronous buck converter is calculated and is compared with conventional buck converter. The studied model of complete system is simulated in the MATLAB/Simulink environment and the results are obtained with closeness to the theoretical study.
{"title":"Modeling, Analysis and Design of Synchronous Buck Converter Using State Space Averaging Technique for PV Energy System","authors":"G. Suman, B. V. S. P. Kumar, M. S. Kumar, B. Babu, K. Subhashini","doi":"10.1109/ISED.2012.27","DOIUrl":"https://doi.org/10.1109/ISED.2012.27","url":null,"abstract":"In this paper, modeling, analysis and design of synchronous buck converter for low power photo-voltaic (PV) energy system is presented. For analyzing the performance such converter, first we studied the characteristics of PV array under different values of irradiance and temperature. Then the exquisite design of synchronous buck converter with the application of State Space Averaging to implement precise control design for the converter is presented. The synchronous buck converter thus designed is used for portable appliances such as mobiles, laptops, iPod's laptops, etc. In addition to that, closed loop control of synchronous buck converter is studied in order to meet the dynamic energy requirement of load especially during variation of source i.e. variation of solar irradiation and temperature. Further, the efficiency of synchronous buck converter is calculated and is compared with conventional buck converter. The studied model of complete system is simulated in the MATLAB/Simulink environment and the results are obtained with closeness to the theoretical study.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133028489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposed a time efficient graph based spatial clustering for large scale GIS data. As volume of GIS data is large, the direct clustering will not be that much efficient in both space and time complexity domains. So, data is preprocessed using Delaunay Triangulation to reduce both the space and time complexities. The preprocessed data is then considered for spanning tree based crisp clustering. The Fuzzy based postprocessing refinement is used to incorporate some extra points. The time and space complexity has been reduced and as a result efficiency of clustering is achieved.
{"title":"A Delaunay Triangulation Preprocessing Based Fuzzy-Encroachment Graph Clustering for Large Scale GIS Data","authors":"Parthajit Roy, J. K. Mandal","doi":"10.1109/ISED.2012.54","DOIUrl":"https://doi.org/10.1109/ISED.2012.54","url":null,"abstract":"This paper proposed a time efficient graph based spatial clustering for large scale GIS data. As volume of GIS data is large, the direct clustering will not be that much efficient in both space and time complexity domains. So, data is preprocessed using Delaunay Triangulation to reduce both the space and time complexities. The preprocessed data is then considered for spanning tree based crisp clustering. The Fuzzy based postprocessing refinement is used to incorporate some extra points. The time and space complexity has been reduced and as a result efficiency of clustering is achieved.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133164708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fault Tolerance is the ability of a system to detect and recover from a fault in the system. By incorporating fault tolerant features in any architecture, reliability and durability of the system increases at the cost of increased hardware. There must be a good tradeoff between cost and system performance. For all critical applications the system must reconfigure itself automatically to continue its normal operation even if any fault occurs. Again adder is the most essential block in any digital architecture. In this article we will design a four bit fault tolerant ripple carry adder and also discuss how design costs and number of faults to be tolerated are affected with the size of sub-module chosen to make the system self-reconfigurable.
{"title":"Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture","authors":"Atin Mukherjee, A. Dhar","doi":"10.1109/ISED.2012.21","DOIUrl":"https://doi.org/10.1109/ISED.2012.21","url":null,"abstract":"Fault Tolerance is the ability of a system to detect and recover from a fault in the system. By incorporating fault tolerant features in any architecture, reliability and durability of the system increases at the cost of increased hardware. There must be a good tradeoff between cost and system performance. For all critical applications the system must reconfigure itself automatically to continue its normal operation even if any fault occurs. Again adder is the most essential block in any digital architecture. In this article we will design a four bit fault tolerant ripple carry adder and also discuss how design costs and number of faults to be tolerated are affected with the size of sub-module chosen to make the system self-reconfigurable.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124744251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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