C. J. Janraj, T. V. Kalyan, Tripti S. Warrier, M. Mutyam
{"title":"Way Sharing Set Associative Cache Architecture","authors":"C. J. Janraj, T. V. Kalyan, Tripti S. Warrier, M. Mutyam","doi":"10.1109/VLSID.2012.79","DOIUrl":null,"url":null,"abstract":"In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit non-uniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2012.79","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit non-uniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty.