The aim of the paper is to develop an efficient circuit simulator to solve circuits arising out of an electrical analogy for Partial Differential Equations (PDEs). This electrical analogy arises when we solve PDE through finite element method (FEM). The paper also proposes an optimal method for simulation of such circuits. We have built simulators based on Modified Nodal Analysis and Two Graph method for solution of PDEs through electrical analogy and compared their timing performance with commercial simulators. The timing performance of circuit simulators is improved for special PDE problems (such as Convection-diffusion) by an efficient implementation of iterative Cholesky with Two Graph method. The method is based on a graph representation of linear systems of equations. Such iterative methods would not be feasible with MNA. Using this method, we have been able to simulate circuits arising from the Convection-Diffusion problem with approximately 1.6 million nodes and 47 million edges in less than 8 minutes.
{"title":"Two Graph Based Circuit Simulator for PDE-Electrical Analogy","authors":"Yogesh Dilip Save, H. Narayanan, S. Patkar","doi":"10.1109/VLSID.2013.214","DOIUrl":"https://doi.org/10.1109/VLSID.2013.214","url":null,"abstract":"The aim of the paper is to develop an efficient circuit simulator to solve circuits arising out of an electrical analogy for Partial Differential Equations (PDEs). This electrical analogy arises when we solve PDE through finite element method (FEM). The paper also proposes an optimal method for simulation of such circuits. We have built simulators based on Modified Nodal Analysis and Two Graph method for solution of PDEs through electrical analogy and compared their timing performance with commercial simulators. The timing performance of circuit simulators is improved for special PDE problems (such as Convection-diffusion) by an efficient implementation of iterative Cholesky with Two Graph method. The method is based on a graph representation of linear systems of equations. Such iterative methods would not be feasible with MNA. Using this method, we have been able to simulate circuits arising from the Convection-Diffusion problem with approximately 1.6 million nodes and 47 million edges in less than 8 minutes.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134049605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The goal of this tutorial is to explain the limits and opportunities of using silicon-photonic link technology for inter-chip and intra-chip communication in manycore systems. Silicon-photonic links have larger bandwidth density and lower energy than equivalent electrical links. In this tutorial, I will first provide an overview of the silicon-photonic device technology and link transceiver/tuning circuits. Using three silicon-photonic network case studies {on-chip tile-to-tile network, process-to-DRAM network and DRAM memory channel, the various silicon-photonic network design issues at the physical level, micro-architecture level and architecture level will be explained in detail. An iterative design process, where we move between these three levels to meet the power-performance specifications under the silicon-photonic technology constraints will also be presented. At the end of the tutorial, attendees will have a broad understanding of the capabilities of silicon-photonic technology, and they will be able to design and analyze silicon-photonic networks for Manycore systems.
{"title":"Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems","authors":"A. Joshi","doi":"10.1109/VLSID.2012.36","DOIUrl":"https://doi.org/10.1109/VLSID.2012.36","url":null,"abstract":"Summary form only given. The goal of this tutorial is to explain the limits and opportunities of using silicon-photonic link technology for inter-chip and intra-chip communication in manycore systems. Silicon-photonic links have larger bandwidth density and lower energy than equivalent electrical links. In this tutorial, I will first provide an overview of the silicon-photonic device technology and link transceiver/tuning circuits. Using three silicon-photonic network case studies {on-chip tile-to-tile network, process-to-DRAM network and DRAM memory channel, the various silicon-photonic network design issues at the physical level, micro-architecture level and architecture level will be explained in detail. An iterative design process, where we move between these three levels to meet the power-performance specifications under the silicon-photonic technology constraints will also be presented. At the end of the tutorial, attendees will have a broad understanding of the capabilities of silicon-photonic technology, and they will be able to design and analyze silicon-photonic networks for Manycore systems.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117062480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
FPGAs have emerged as the preferred prototyping and accelerator platform for diverse application domains such as digital signal processing (DSP), security and multimedia, which often impose real-time performance requirements. Most applications in these domains require efficient implementation of complex data paths or functions, e.g. transcendental functions which are spatially mapped in the configurable logic or embedded DSP blocks of a FPGA device. Requirement of elaborate computational resources to realize these operations impose a major barrier to energy efficiency. In this paper, we propose to use embedded memory blocks in FPGA for computing to significantly improve energy efficiency of the applications which are dominated by complex data paths and/or functions. Complex operations are decomposed into large multi-input/output lookup tables (LUTs); mapped to embedded memory blocks and evaluated through memory access over single or multiple cycles. Different parts of an application are selectively mapped into memory or logic/DSP blocks in a heterogeneous mapping framework to maximize energy efficiency. We explore optimal energy configuration of embedded memory for mapping applications of varying input size and develop a complete mapping flow including decomposition, fusion and packing. Effectiveness of the proposed flow is evaluated using a commercial state-of-the-art FPGA system (Altera Stratix IV device). Finally the proposed framework is used to drastically trade-off energy vs accuracy at run-time for common signal processing applications.
{"title":"Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks","authors":"A. Ghosh, Somnath Paul, S. Bhunia","doi":"10.1109/VLSID.2012.108","DOIUrl":"https://doi.org/10.1109/VLSID.2012.108","url":null,"abstract":"FPGAs have emerged as the preferred prototyping and accelerator platform for diverse application domains such as digital signal processing (DSP), security and multimedia, which often impose real-time performance requirements. Most applications in these domains require efficient implementation of complex data paths or functions, e.g. transcendental functions which are spatially mapped in the configurable logic or embedded DSP blocks of a FPGA device. Requirement of elaborate computational resources to realize these operations impose a major barrier to energy efficiency. In this paper, we propose to use embedded memory blocks in FPGA for computing to significantly improve energy efficiency of the applications which are dominated by complex data paths and/or functions. Complex operations are decomposed into large multi-input/output lookup tables (LUTs); mapped to embedded memory blocks and evaluated through memory access over single or multiple cycles. Different parts of an application are selectively mapped into memory or logic/DSP blocks in a heterogeneous mapping framework to maximize energy efficiency. We explore optimal energy configuration of embedded memory for mapping applications of varying input size and develop a complete mapping flow including decomposition, fusion and packing. Effectiveness of the proposed flow is evaluated using a commercial state-of-the-art FPGA system (Altera Stratix IV device). Finally the proposed framework is used to drastically trade-off energy vs accuracy at run-time for common signal processing applications.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127339137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. J. Janraj, T. V. Kalyan, Tripti S. Warrier, M. Mutyam
In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit non-uniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty.
{"title":"Way Sharing Set Associative Cache Architecture","authors":"C. J. Janraj, T. V. Kalyan, Tripti S. Warrier, M. Mutyam","doi":"10.1109/VLSID.2012.79","DOIUrl":"https://doi.org/10.1109/VLSID.2012.79","url":null,"abstract":"In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit non-uniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117039009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Redundant binary (RB) number systems are becoming popular because of its unique carry propagation free addition property. A finite impulse response (FIR) filter computes its output using multiply and accumulate operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only two partial product rows are obtained in RB form for each input and coefficient multiplications. These two partial product rows are added using carry free RB addition. Finally the RB output is converted back to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier architecture for FIR filter is compared with computation sharing multiplier (CSHM) implementation in 90nm technology. The proposed multiplication method for FIR filter is found to be faster approximately by 42% in comparison to CSHM implementation, however with 0.5% and 11% increase in area and power respectively.
{"title":"A High Speed FIR Filter Architecture Based on Novel Higher Radix Algorithm","authors":"S. K. Sahoo, K. S. Reddy","doi":"10.1109/VLSID.2012.48","DOIUrl":"https://doi.org/10.1109/VLSID.2012.48","url":null,"abstract":"Redundant binary (RB) number systems are becoming popular because of its unique carry propagation free addition property. A finite impulse response (FIR) filter computes its output using multiply and accumulate operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only two partial product rows are obtained in RB form for each input and coefficient multiplications. These two partial product rows are added using carry free RB addition. Finally the RB output is converted back to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier architecture for FIR filter is compared with computation sharing multiplier (CSHM) implementation in 90nm technology. The proposed multiplication method for FIR filter is found to be faster approximately by 42% in comparison to CSHM implementation, however with 0.5% and 11% increase in area and power respectively.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129098133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Analyzing poles and zeros of a circuit is often essential for (a) choose the appropriate topology for given specifications, (b) understanding the frequency response of the circuit and (c) stabilizing the circuit by choosing appropriate frequency compensation techniques. Analyzing poles and zeros of a low-dropout (LDO) voltage regulator is often intriguing as (a) the voltage/current control loop need to be broken for small signal analysis and (b) the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. During the process, several frequency compensation techniques are elucidated.
{"title":"Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview","authors":"A. Garimella, Punith R. Surkanti, P. Furth","doi":"10.1109/VLSID.2012.38","DOIUrl":"https://doi.org/10.1109/VLSID.2012.38","url":null,"abstract":"Analyzing poles and zeros of a circuit is often essential for (a) choose the appropriate topology for given specifications, (b) understanding the frequency response of the circuit and (c) stabilizing the circuit by choosing appropriate frequency compensation techniques. Analyzing poles and zeros of a low-dropout (LDO) voltage regulator is often intriguing as (a) the voltage/current control loop need to be broken for small signal analysis and (b) the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. During the process, several frequency compensation techniques are elucidated.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123991661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nano-electromechanical (NEM) relays are a promising class of emerging devices that exhibit zero leakage operation. Numerous end applications of NEM relay logic circuits have been proposed recently [1][2]. This work explores the usage of NEM relays in on-chip DC-DC converters. As a feasibility study of using NEMS in integrated power electronics, discontinuous conduction mode (DCM) buck regulator with specifications suitable for portable applications has been implemented in a NEMS-CMOS hybrid design and the results are compared against a standard commercial 0.35 μm CMOS implementation. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Accurate Verilog-A models were developed based on published fabrication results of NEM relays [1] operating at 1V with a nominal air gap of 5-10nm. This work shows that NEMS-CMOS hybrid DC-DC converter has an area savings of 60V over CMOS and achieves 95% efficiency at max load condition (50mA).
{"title":"Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency","authors":"S. Manohar, R. Venkatasubramanian, P. Balsara","doi":"10.1109/VLSID.2012.74","DOIUrl":"https://doi.org/10.1109/VLSID.2012.74","url":null,"abstract":"Nano-electromechanical (NEM) relays are a promising class of emerging devices that exhibit zero leakage operation. Numerous end applications of NEM relay logic circuits have been proposed recently [1][2]. This work explores the usage of NEM relays in on-chip DC-DC converters. As a feasibility study of using NEMS in integrated power electronics, discontinuous conduction mode (DCM) buck regulator with specifications suitable for portable applications has been implemented in a NEMS-CMOS hybrid design and the results are compared against a standard commercial 0.35 μm CMOS implementation. Ron of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite Roff offers significant area and power advantages over CMOS. Accurate Verilog-A models were developed based on published fabrication results of NEM relays [1] operating at 1V with a nominal air gap of 5-10nm. This work shows that NEMS-CMOS hybrid DC-DC converter has an area savings of 60V over CMOS and achieves 95% efficiency at max load condition (50mA).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134085260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dynamic power dissipation in interconnects is a major contributor to power consumption in Network on Chips (NoCs). This is mainly due to two factors, self switching activity of the particular link and coupling switching activity among adjacent links. Two novel techniques are proposed to reduce power consumption due to switching transition and cross talk. First technique reorders the data in such a way that switching transition is brought down. In the second technique, it is ensured that power consumption due to cross coupling activity is reduced. An end to end encoding scheme facilitating two stage coding to reduce power consumption in wormhole routed network on chip is designed using the proposed power reduction techniques. Encoder and Decoder exhibiting the proposed scheme have been described in RTL level in Verilog HDL, synthesized and mapped into UMC180 nm technology library. It has been observed that the proposed technique (TSC) offers an average reduction in dynamic power consumption of 17.34%. Proposed scheme was compared with existing techniques and observations concluded that there was not much degradation in area, speed and static power dissipation. Power reduction when subjected to different kinds of data streams was analyzed and results indicate that proposed scheme offers uniform power reduction irrespective of the nature of data stream unlike the existing techniques.
{"title":"A Novel Encoding Scheme for Low Power in Network on Chip Links","authors":"Deepa N. Sarma, G. Lakshminarayanan, K. Chavali","doi":"10.1109/VLSID.2012.80","DOIUrl":"https://doi.org/10.1109/VLSID.2012.80","url":null,"abstract":"Dynamic power dissipation in interconnects is a major contributor to power consumption in Network on Chips (NoCs). This is mainly due to two factors, self switching activity of the particular link and coupling switching activity among adjacent links. Two novel techniques are proposed to reduce power consumption due to switching transition and cross talk. First technique reorders the data in such a way that switching transition is brought down. In the second technique, it is ensured that power consumption due to cross coupling activity is reduced. An end to end encoding scheme facilitating two stage coding to reduce power consumption in wormhole routed network on chip is designed using the proposed power reduction techniques. Encoder and Decoder exhibiting the proposed scheme have been described in RTL level in Verilog HDL, synthesized and mapped into UMC180 nm technology library. It has been observed that the proposed technique (TSC) offers an average reduction in dynamic power consumption of 17.34%. Proposed scheme was compared with existing techniques and observations concluded that there was not much degradation in area, speed and static power dissipation. Power reduction when subjected to different kinds of data streams was analyzed and results indicate that proposed scheme offers uniform power reduction irrespective of the nature of data stream unlike the existing techniques.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131020124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a hybrid temperature sensing resistive random access memory (TSRRAM) architecture composed of traditional CMOS components and emerging memristive switching devices. The architecture enables each RRAM switching element to be used both as a memory bit and a temperature sensor. The TSRRAM is integrated into an Alpha 21364 processor as an L2 cache. Its accuracy and performance were simulated using a customized simulation framework. SPEC2000 benchmarks were used to generate thermal profiles in the Alpha processor core. Active and passive sensing mechanisms are also introduced as means for DTM algorithms to determine the thermal profile of the RRAM switching layer. The proposed architecture yielded a 2.14 K mean absolute temperature error during passive sensing, which is well within the useful range of dynamic thermal management (DTM) algorithms. Furthermore, the proposed design is shown to have only an 8 cycle performance overhead.
{"title":"Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures","authors":"Cory E. Merkel, D. Kudithipudi","doi":"10.1109/VLSID.2012.65","DOIUrl":"https://doi.org/10.1109/VLSID.2012.65","url":null,"abstract":"In this paper, we propose a hybrid temperature sensing resistive random access memory (TSRRAM) architecture composed of traditional CMOS components and emerging memristive switching devices. The architecture enables each RRAM switching element to be used both as a memory bit and a temperature sensor. The TSRRAM is integrated into an Alpha 21364 processor as an L2 cache. Its accuracy and performance were simulated using a customized simulation framework. SPEC2000 benchmarks were used to generate thermal profiles in the Alpha processor core. Active and passive sensing mechanisms are also introduced as means for DTM algorithms to determine the thermal profile of the RRAM switching layer. The proposed architecture yielded a 2.14 K mean absolute temperature error during passive sensing, which is well within the useful range of dynamic thermal management (DTM) algorithms. Furthermore, the proposed design is shown to have only an 8 cycle performance overhead.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132876342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A compact (0.1 mm2 area) temperature-recording system that is suitable for easy integration into an SOC is described. It includes a PTAT sensor, a pre-amplifier, and a first-order sigma-delta modulator based ADC all operating at 1.2V supply. The switched-capacitor pre-amplifier uses an auto-zeroing scheme based upon capacitive reset to avoid the need for shorting the op-amp outputs and inputs during reset. Errors due to transistor leakage are eliminated by selective use of thick-oxide transistors in the design. Another contribution of the paper is to illustrate a scheme that uses two reference voltages in the sigma-delta modulator ADC corresponding to the minimum and maximum temperatures measured to improve its effective resolution.
{"title":"A Compact Temperature Sensor at 1.8µA per Hz Conversion Rate and 1.1 °C Accuracy for SOCs","authors":"S. Sen, D. Babitch, N. Dubash","doi":"10.1109/VLSID.2012.67","DOIUrl":"https://doi.org/10.1109/VLSID.2012.67","url":null,"abstract":"A compact (0.1 mm2 area) temperature-recording system that is suitable for easy integration into an SOC is described. It includes a PTAT sensor, a pre-amplifier, and a first-order sigma-delta modulator based ADC all operating at 1.2V supply. The switched-capacitor pre-amplifier uses an auto-zeroing scheme based upon capacitive reset to avoid the need for shorting the op-amp outputs and inputs during reset. Errors due to transistor leakage are eliminated by selective use of thick-oxide transistors in the design. Another contribution of the paper is to illustrate a scheme that uses two reference voltages in the sigma-delta modulator ADC corresponding to the minimum and maximum temperatures measured to improve its effective resolution.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132294605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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