Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs

Abstract

This paper explores the concept of Design Diversity Redundancy applied to SRAM-based FPGAs as a proposal to decrease failure rate. A 32-bit RISC processor MIPS was protected by coarse grain Triple Modular Redundancy (TMR) and by Diverse TMR (DTMR). Experimental results under neutron flux radiation show that DTMR can reduce in 40% the Failure in Time (FIT) of a system when compared to the standard MIPS while the coarse gain TMR could reduce the FIT in only 10%.