Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962088
M. Skitsas, C. Nicopoulos, M. Michael
As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, we investigate the relation between system test latency and testtime overhead in multi-/many-core systems with shared LastLevel Cache (LLC) for periodic Software-Based Self-Testing (SBST), under different test scheduling policies. The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system testing session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relation between the two test measures; as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for running normal workloads. Under given system test latency constraints, which should be utilized in order to be able to control system recovery time in the event of an error detection, our exploration framework identifies the scheduling policy under which overall test time overhead is minimized and, hence, system availability is maximized. Without any loss of generality, a 16-core system is explored in a full-system, execution-driven simulation framework running multi-threaded PARSEC workloads [1].
{"title":"Exploration of system availability during software-based self-testing in many-core systems under test latency constraints","authors":"M. Skitsas, C. Nicopoulos, M. Michael","doi":"10.1109/DFT.2014.6962088","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962088","url":null,"abstract":"As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, we investigate the relation between system test latency and testtime overhead in multi-/many-core systems with shared LastLevel Cache (LLC) for periodic Software-Based Self-Testing (SBST), under different test scheduling policies. The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system testing session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relation between the two test measures; as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for running normal workloads. Under given system test latency constraints, which should be utilized in order to be able to control system recovery time in the event of an error detection, our exploration framework identifies the scheduling policy under which overall test time overhead is minimized and, hence, system availability is maximized. Without any loss of generality, a 16-core system is explored in a full-system, execution-driven simulation framework running multi-threaded PARSEC workloads [1].","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115647409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962079
Swapnil Bahl, Shrey Rungta, Shray Khullar, R. Kapur, A. Chandra, S. Talluto, Pramod Notiyath, Ajay Rajagopalan
STMicroelectronics has been using scan compression for many years. With the vast variety of designs and the size of the company it is important to deploy an easy to use solution that works for all the conditions. Today we support many different compression schemes DFTMAX, DFTMAX Xtol, Serializer. Each of these solutions is strong in a segment of the designs. DFTMAX Ultra has a technology that provides a single solution for all needs. In this paper we discuss the variety of design scenarios seen in ST from the point of scan compression. Results of DFTMAX Ultra are then presented to show that it is a viable unified solution.
{"title":"Unifying scan compression","authors":"Swapnil Bahl, Shrey Rungta, Shray Khullar, R. Kapur, A. Chandra, S. Talluto, Pramod Notiyath, Ajay Rajagopalan","doi":"10.1109/DFT.2014.6962079","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962079","url":null,"abstract":"STMicroelectronics has been using scan compression for many years. With the vast variety of designs and the size of the company it is important to deploy an easy to use solution that works for all the conditions. Today we support many different compression schemes DFTMAX, DFTMAX Xtol, Serializer. Each of these solutions is strong in a segment of the designs. DFTMAX Ultra has a technology that provides a single solution for all needs. In this paper we discuss the variety of design scenarios seen in ST from the point of scan compression. Results of DFTMAX Ultra are then presented to show that it is a viable unified solution.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126740937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962097
M. He, M. Tehranipoor
With technology scaling, the number of sensors integrated into modern system-on-chip (SoC) designs has increased greatly over the past several years. These sensors must be accessed for a number of reasons (test, configuration, calibration, etc.). This paper proposes a novel sensor access mechanism (SAM) to address sensor access in various modes, including manufacturing test mode, functional mode, built-in self-test (BIST) mode, silicon validation mode, and calibration mode. Moreover, SAM standardizes the testing and measurement of embedded sensors by providing easy and effective access to sensors distributed across the SoC. Further, SAM does not introduce a new pin, making it JTAG compatible and practice-oriented for easy industrial adoption. Various simulation results, collected by integrating SAM into several benchmarks demonstrate its high performance and low overhead.
{"title":"SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs","authors":"M. He, M. Tehranipoor","doi":"10.1109/DFT.2014.6962097","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962097","url":null,"abstract":"With technology scaling, the number of sensors integrated into modern system-on-chip (SoC) designs has increased greatly over the past several years. These sensors must be accessed for a number of reasons (test, configuration, calibration, etc.). This paper proposes a novel sensor access mechanism (SAM) to address sensor access in various modes, including manufacturing test mode, functional mode, built-in self-test (BIST) mode, silicon validation mode, and calibration mode. Moreover, SAM standardizes the testing and measurement of embedded sensors by providing easy and effective access to sensors distributed across the SoC. Further, SAM does not introduce a new pin, making it JTAG compatible and practice-oriented for easy industrial adoption. Various simulation results, collected by integrating SAM into several benchmarks demonstrate its high performance and low overhead.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114855056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962096
Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, M. Tehranipoor
The globalization of the semiconductor design and fabrication industry (also known as the horizontal business model) has led to many well-documented issues associated with untrusted foundries and assemblies, including IC overproduction, cloning, and the shipping of improperly or insufficiently tested chips. Besides the loss in profits to Intellectual Property (IP) owners, such chips entering the supply chain can have catastrophic consequences for critical applications. We propose a new Secure Split-Test (SST) scheme called the Connecticut SST (CSST) in which the IP owner takes full control over testing. In CSST, each chip and its scan chains are locked during testing, and only the IP owner can interpret the locked test results and unlock passing chips. The new SST can prevent overproduced, defective, and cloned chips from reaching the supply chain. The proposed method considerably simplifies the communication required between the foundry/assembly and the IP owner compared to the original version of the SST. The results demonstrate that our new technique is more secure than the original and has lower communication overheads.
{"title":"CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly","authors":"Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, M. Tehranipoor","doi":"10.1109/DFT.2014.6962096","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962096","url":null,"abstract":"The globalization of the semiconductor design and fabrication industry (also known as the horizontal business model) has led to many well-documented issues associated with untrusted foundries and assemblies, including IC overproduction, cloning, and the shipping of improperly or insufficiently tested chips. Besides the loss in profits to Intellectual Property (IP) owners, such chips entering the supply chain can have catastrophic consequences for critical applications. We propose a new Secure Split-Test (SST) scheme called the Connecticut SST (CSST) in which the IP owner takes full control over testing. In CSST, each chip and its scan chains are locked during testing, and only the IP owner can interpret the locked test results and unlock passing chips. The new SST can prevent overproduced, defective, and cloned chips from reaching the supply chain. The proposed method considerably simplifies the communication required between the foundry/assembly and the IP owner compared to the original version of the SST. The results demonstrate that our new technique is more secure than the original and has lower communication overheads.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115858001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962093
S. Carlo, Marco Indaco, P. Prinetto, E. Vatajelu, R. Rodríguez-Montañés, J. Figueras
In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve the desired reliability target for the memory under study.
{"title":"Reliability estimation at block-level granularity of spin-transfer-torque MRAMs","authors":"S. Carlo, Marco Indaco, P. Prinetto, E. Vatajelu, R. Rodríguez-Montañés, J. Figueras","doi":"10.1109/DFT.2014.6962093","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962093","url":null,"abstract":"In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve the desired reliability target for the memory under study.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117249714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962100
Manoj Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, M. Ebrahimi, Mark Zwolinski
Networks-on-Chip (NoCs) are emerging as a promising communication paradigm to overcome bottleneck of traditional bus-based interconnects for current microarchitectures (MCSoC and CMP). One of the known current problems in NoC routing is the use of acyclic Channel Dependency Graph (CDG) for deadlock freedom. This requirement forces certain routing turns to be prohibited, thus, reducing the degree of adaptiveness. In this paper, we propose a novel non-minimal turn model which allows cycles in CDG provided that Extended Channel Dependency Graph (ECDG) remains acyclic. The proposed turn model reduces number of restrictions on routing turns, hence able to provide path diversity through additional minimal and non-minimal routes between source and destination. We also develop a fault tolerant and congestion-aware routing algorithm based on the proposed turn model to demonstrate the effectiveness. In this algorithm, a non-minimal route is used only when links in minimal routes are congested or faulty. Average performance gain of the proposed method is up to 26% across all selected benchmarks when compared with DRFT and 12% when compared with LEAR for 7 × 7 mesh.
{"title":"Fault tolerant and highly adaptive routing for 2D NoCs","authors":"Manoj Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, M. Ebrahimi, Mark Zwolinski","doi":"10.1109/DFT.2014.6962100","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962100","url":null,"abstract":"Networks-on-Chip (NoCs) are emerging as a promising communication paradigm to overcome bottleneck of traditional bus-based interconnects for current microarchitectures (MCSoC and CMP). One of the known current problems in NoC routing is the use of acyclic Channel Dependency Graph (CDG) for deadlock freedom. This requirement forces certain routing turns to be prohibited, thus, reducing the degree of adaptiveness. In this paper, we propose a novel non-minimal turn model which allows cycles in CDG provided that Extended Channel Dependency Graph (ECDG) remains acyclic. The proposed turn model reduces number of restrictions on routing turns, hence able to provide path diversity through additional minimal and non-minimal routes between source and destination. We also develop a fault tolerant and congestion-aware routing algorithm based on the proposed turn model to demonstrate the effectiveness. In this algorithm, a non-minimal route is used only when links in minimal routes are congested or faulty. Average performance gain of the proposed method is up to 26% across all selected benchmarks when compared with DRFT and 12% when compared with LEAR for 7 × 7 mesh.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129629642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962106
S. Tzilis, I. Sourdis
The increasing number of transistors integrated on a single chip comes with the blessing of raw computational power and the curse of susceptibility to various kinds of faults. On top of increased defect densities, wearout effects mean that the testing verdict at fabrication time cannot be trusted throughout the chip lifetime. However, extra computational power presents the opportunity to build gracefully degrading MPSoCs. Re-configurable components and flexible workloads, along with runtime support, enable MPSoCs to deal with permanent faults degrading one or more system aspects, such as performance, energy efficiency and delivered functionality, instead of failing. In this manner, chip life is prolonged and safety is increased. In this work Graceful Degradation (GD) is formulated as an optimization problem in the context of MPSoCs. As such, its possible solutions can be evaluated in a parameterizable and consistent manner. An attempt at a runtime solution for a heterogeneous 4-core SoC is made and the resulting GD manager is evaluated in terms of speed and accuracy, with a use case combining essential automotive tasks and non-essential additional features. On average, it is found to produce a solution 89% as good as the optimal, in 4.3μsec running on one core of a common modern CPU.
{"title":"A runtime manager for gracefully degrading SoCs","authors":"S. Tzilis, I. Sourdis","doi":"10.1109/DFT.2014.6962106","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962106","url":null,"abstract":"The increasing number of transistors integrated on a single chip comes with the blessing of raw computational power and the curse of susceptibility to various kinds of faults. On top of increased defect densities, wearout effects mean that the testing verdict at fabrication time cannot be trusted throughout the chip lifetime. However, extra computational power presents the opportunity to build gracefully degrading MPSoCs. Re-configurable components and flexible workloads, along with runtime support, enable MPSoCs to deal with permanent faults degrading one or more system aspects, such as performance, energy efficiency and delivered functionality, instead of failing. In this manner, chip life is prolonged and safety is increased. In this work Graceful Degradation (GD) is formulated as an optimization problem in the context of MPSoCs. As such, its possible solutions can be evaluated in a parameterizable and consistent manner. An attempt at a runtime solution for a heterogeneous 4-core SoC is made and the resulting GD manager is evaluated in terms of speed and accuracy, with a use case combining essential automotive tasks and non-essential additional features. On average, it is found to produce a solution 89% as good as the optimal, in 4.3μsec running on one core of a common modern CPU.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130639163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962073
S. Carlo, P. Prinetto, Daniele Rolfo, Pascal Trotta
Modern SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly employed in safety- and mission-critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. Assessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing design exploration of different protection alternatives. This paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated infrastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.
{"title":"A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs","authors":"S. Carlo, P. Prinetto, Daniele Rolfo, Pascal Trotta","doi":"10.1109/DFT.2014.6962073","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962073","url":null,"abstract":"Modern SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly employed in safety- and mission-critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. Assessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing design exploration of different protection alternatives. This paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated infrastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126462725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962081
Bahareh J. Farahani, S. Safari
As semiconductor technology has entered into the nanoscale regime, Single Event Transient (SET) became one of the major challenging issues for silicon chips. Susceptibility to soft error is even becoming more severe in the presence of Process, Voltage, Temperature, and transistor Aging (PVTA) variations. In this paper, we model and analyze the impacts of PVTA on the susceptibility of VLSI chips to SET. We show that higher PVTA results in significant reduction of critical charge (i.e, higher glitch generation) of silicons while electrical masking (preventing glitch propagation) is improved. In addition, we propose a holistic instance-based systematic methodology to calculate the Soft Error Rate (SER) of combinationals considering PVTA variations. The simulation results for various ITC'99 benchmark circuits show that disregarding PVTA information results in 76% error in the estimated SER on average. Moreover, according to the results, SER increases by 70% on average in the first years of circuit lifetime due to transistor aging and then it is almost saturated.
{"title":"An instance-based SER analysis in the presence of PVTA variations","authors":"Bahareh J. Farahani, S. Safari","doi":"10.1109/DFT.2014.6962081","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962081","url":null,"abstract":"As semiconductor technology has entered into the nanoscale regime, Single Event Transient (SET) became one of the major challenging issues for silicon chips. Susceptibility to soft error is even becoming more severe in the presence of Process, Voltage, Temperature, and transistor Aging (PVTA) variations. In this paper, we model and analyze the impacts of PVTA on the susceptibility of VLSI chips to SET. We show that higher PVTA results in significant reduction of critical charge (i.e, higher glitch generation) of silicons while electrical masking (preventing glitch propagation) is improved. In addition, we propose a holistic instance-based systematic methodology to calculate the Soft Error Rate (SER) of combinationals considering PVTA variations. The simulation results for various ITC'99 benchmark circuits show that disregarding PVTA information results in 76% error in the estimated SER on average. Moreover, according to the results, SER increases by 70% on average in the first years of circuit lifetime due to transistor aging and then it is almost saturated.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133411836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962104
Prashant D. Joshi, S. Hamdioui
Many routing protocols make some assumptions on the correctness of the routing information in the router. This at times allows faults and malicious attacks in the networks. This paper describes a class of networks based on modified line graphs with many features to authenticate the data and controls of the message routing, and having properties of the shortest diameters and easy shortest path calculations. We describe this class of fault tolerant networks and the relevant properties. This helps understand the security mechanism, WISH ('What I See and Hear') that probes the data and the routing information to reduce the possibility of router problems, malicious or otherwise.
{"title":"Security methods in fault tolerant modified line graph based networks","authors":"Prashant D. Joshi, S. Hamdioui","doi":"10.1109/DFT.2014.6962104","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962104","url":null,"abstract":"Many routing protocols make some assumptions on the correctness of the routing information in the router. This at times allows faults and malicious attacks in the networks. This paper describes a class of networks based on modified line graphs with many features to authenticate the data and controls of the message routing, and having properties of the shortest diameters and easy shortest path calculations. We describe this class of fault tolerant networks and the relevant properties. This helps understand the security mechanism, WISH ('What I See and Hear') that probes the data and the routing information to reduce the possibility of router problems, malicious or otherwise.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126263749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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