Seung-Moon Yoo, Jin-Man Han, E. Haq, S. Yoon, Se-Jin Jeong, Byungchan Kim, Jung-Hwa Lee, Tae-Seong Jang, Hyung-Dong Kim, C. Park, D.I. Seo, C. S. Choi, Sooin Cho, C. Hwang
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引用次数: 12
Abstract
A 256M DRAM featuring register controlled low power self refresh without toggling of internal addresses or predecoders, activation of all row lines in quick succession for rapid burn-in at wafer level and hierarchical I/O line scheme with flexible redundancy is developed. The 13.75 x 23.86 mm2 die size, 16M x16 DRAM with 3811s access time at 2.2V and 70 "C has been fabricated using 0.25pm triple well CMOS technology.
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