Robust architecture for locally-clocked extended burst-mode circuits without timing assumption

Abstract

Asynchronous controllers based on Asynchronous Finite State Machines (AFSM) are widely used in the control unit design of asynchronous systems. These systems can be implemented in Field Programmable Gate Arrays (FPGAs), which are a low cost design alternative. Different styles have been proposed to implement AFSMs, but all of them have limitations when implemented in FPGAs. Therefore, this paper proposes a novel architecture for AFSMs in the local clock style. AFSMs are described in the extended burst-mode (XBM) specification. The existence of a local clock reduces the requirements of asynchronous logic, but the timing requirements may require the insertion of delays, which makes FPGA implementation difficult and leads to degradation of performance and reliability. The novel proposed local clock architecture is robust to setup and hold time violations, so they are free of timing analysis and do not need to introduce any kind of delays. The proposed architecture was applied to thirteen benchmarks and when compared to the local clock architecture of SICARELO tool, focused on FPGAs, it did not need to introduce any delays, whereas SICARELO had to introduce delays in all thirteen benchmarks of up to 4.9ns and there was an average reduction of 30% at the time of latency.