Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication

2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI:10.1109/SOCC.2006.283840

Hongjiang Song

引用次数: 2

Abstract

A low power, small area receiver equalizer circuit based on novel threshold multiplexing (TMX) technique is presented. Simulation results based on the proposed sampler circuit and a 3-level 2-tap TMX equalizer circuit implementation show achievable 20~30 ps eye margin improvement for a 5 Gb/s high-speed serial I/O application. This circuit demonstrates a very low PVT sensitivity and extremely wideband operation, which is fully digital and highly scalable and therefore very suitable for SOC applications.

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高速串行数据通信中功率和面积有效的接收机均衡电路的结构与实现

提出了一种基于新型阈值复用(TMX)技术的低功耗小面积接收机均衡器电路。仿真结果表明，基于所提出的采样器电路和一个3电平2抽头TMX均衡器电路实现，对于5gb /s高速串行I/O应用，眼余量可提高20~ 30ps。该电路具有非常低的PVT灵敏度和极宽带操作，完全数字化和高度可扩展，因此非常适合SOC应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2006 IEEE International SOC Conference

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