Supreet Jeloka, B. Cline, Shidhartha Das, Benoît Labbé, Alejandro Rico, R. Herberholz, Javier A. DeLaCruz, R. Mathur, S. Hung
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引用次数: 2
Abstract
As Moore's law fades and scaling of logic, memory and interconnects diverge, 3D integration technologies have become one of the primary approaches to maintaining performance gains in SoCs and SiPs. To fully exploit the system-level performance gains from 3D, we need to co-optimize the 3D system design for the 3D integration technology used, as well as solve the major physical design challenges of system partitioning, power delivery, thermals, and timing for 3D ICs. In this paper we will cover the system technology co-optimization and design challenges for 3D ICs from high-performance 3D CPU to many-core 3D system design.
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