Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772832
Atefeh Sohrabizadeh, Yuze Chi, J. Cong
While there have been many studies on hardware acceleration for deep learning on images, there has been a rather limited focus on accelerating deep learning applications involving graphs. The unique characteristics of graphs, such as the irregular memory access and dynamic parallelism, impose several challenges when the algorithm is mapped to a CPU or GPU. To address these challenges while exploiting all the available sparsity, we propose a flexible architecture called StreamGCN for accelerating Graph Convolutional Networks (GCN), the core computation unit in deep learning algorithms on graphs. The architecture is specialized for streaming processing of many small graphs for graph search and similarity computation. The experimental results demonstrate that StreamGCN can deliver a high speedup compared to a multi-core CPU and a GPU implementation, showing the efficiency of our design.
{"title":"StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing","authors":"Atefeh Sohrabizadeh, Yuze Chi, J. Cong","doi":"10.1109/CICC53496.2022.9772832","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772832","url":null,"abstract":"While there have been many studies on hardware acceleration for deep learning on images, there has been a rather limited focus on accelerating deep learning applications involving graphs. The unique characteristics of graphs, such as the irregular memory access and dynamic parallelism, impose several challenges when the algorithm is mapped to a CPU or GPU. To address these challenges while exploiting all the available sparsity, we propose a flexible architecture called StreamGCN for accelerating Graph Convolutional Networks (GCN), the core computation unit in deep learning algorithms on graphs. The architecture is specialized for streaming processing of many small graphs for graph search and similarity computation. The experimental results demonstrate that StreamGCN can deliver a high speedup compared to a multi-core CPU and a GPU implementation, showing the efficiency of our design.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125677820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772800
M. Nagatani, H. Wakita, Teruo Jyo, Tsutomu Takeya, H. Yamazaki, Y. Ogiso, M. Mutoh, Y. Shiratori, M. Ida, F. Hamaoka, M. Nakamura, Takayuki Kobayashi, Hiroyuki Takahashi, Y. Miyamoto
To cope with the rapid growth of communications traffic, 400-Gb/s/ch digital coherent systems are being deployed in optical core networks. However, further scaling is required, and the transmission capacity per channel is expected to exceed 1 Tb/s in the near future to sustain the ever-growing traffic. One of the most significant challenges in achieving a channel capacity of beyond 1 Tb/s is to extend the analog bandwidth of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) in the optical transceiver. This paper describes InP-HBT-based ultra-broadband analog multiplexer (AMUX) and analog de-multiplexer (ADEMUX) circuits that can extend the analog bandwidth of DACs and ADCs, respectively. In addition, experimental demonstrations of beyond-1-Tb/s/ch optical modulations and transmissions are addressed.
{"title":"110-GHz-Bandwidth InP-HBT AMUX/ADEMUX Circuits for Beyond-1-Tb/s/ch Digital Coherent Optical Transceivers","authors":"M. Nagatani, H. Wakita, Teruo Jyo, Tsutomu Takeya, H. Yamazaki, Y. Ogiso, M. Mutoh, Y. Shiratori, M. Ida, F. Hamaoka, M. Nakamura, Takayuki Kobayashi, Hiroyuki Takahashi, Y. Miyamoto","doi":"10.1109/CICC53496.2022.9772800","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772800","url":null,"abstract":"To cope with the rapid growth of communications traffic, 400-Gb/s/ch digital coherent systems are being deployed in optical core networks. However, further scaling is required, and the transmission capacity per channel is expected to exceed 1 Tb/s in the near future to sustain the ever-growing traffic. One of the most significant challenges in achieving a channel capacity of beyond 1 Tb/s is to extend the analog bandwidth of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) in the optical transceiver. This paper describes InP-HBT-based ultra-broadband analog multiplexer (AMUX) and analog de-multiplexer (ADEMUX) circuits that can extend the analog bandwidth of DACs and ADCs, respectively. In addition, experimental demonstrations of beyond-1-Tb/s/ch optical modulations and transmissions are addressed.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122434152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772776
Bingzheng Yang, H. Qian, Yiyang Shu, Jie Zhou, Xun Luo
The low cost power amplifiers (PAs) with power back-off (PBO) efficiency enhancement are dramatically demanded in modern wireless communication. The CMOS digital PAs (DPAs) and digital transmitters (TXs) [1]–[7] are developed due to the merits of high efficiency, high integration, and low cost. To achieve higher date rate, the quadrature digital TXs are preferred, which do not need the CORDIC and phase modulator in polar TXs. To improve deep PBO efficiency of DPA, the Class-G Doherty [3], hybrid Doherty with impedance boosting [4], load modulation [5], switched transformer [6], switched/floated capacitor power amplifier (SFCPA) [7], etc. are developed. To further enhance ultra-deep PBO efficiency, a watt-level triple-mode quadrature SFCPA with 56 efficiency peaks using IQ intrinsic impedance interaction and adaptive phase compensation is proposed, which achieves efficiency enhancement at 0/2/3/6/8/9/12/14/15/18/21dB PBOs.
{"title":"Watt-Level Triple-Mode Quadrature SFCPA with 56 Peaks for Ultra-Deep PBO Efficiency Enhancement Using IQ Intrinsic Interaction and Adaptive Phase Compensation","authors":"Bingzheng Yang, H. Qian, Yiyang Shu, Jie Zhou, Xun Luo","doi":"10.1109/CICC53496.2022.9772776","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772776","url":null,"abstract":"The low cost power amplifiers (PAs) with power back-off (PBO) efficiency enhancement are dramatically demanded in modern wireless communication. The CMOS digital PAs (DPAs) and digital transmitters (TXs) [1]–[7] are developed due to the merits of high efficiency, high integration, and low cost. To achieve higher date rate, the quadrature digital TXs are preferred, which do not need the CORDIC and phase modulator in polar TXs. To improve deep PBO efficiency of DPA, the Class-G Doherty [3], hybrid Doherty with impedance boosting [4], load modulation [5], switched transformer [6], switched/floated capacitor power amplifier (SFCPA) [7], etc. are developed. To further enhance ultra-deep PBO efficiency, a watt-level triple-mode quadrature SFCPA with 56 efficiency peaks using IQ intrinsic impedance interaction and adaptive phase compensation is proposed, which achieves efficiency enhancement at 0/2/3/6/8/9/12/14/15/18/21dB PBOs.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114483810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772821
E. Choi, Injun Choi, Chanhee Jeon, Gichan Yun, Donghyeon Yi, S. Ha, I. Chang, M. Je
Over the years, SRAM-based compute-in-memory (CIM) structures have shown ways to perform deep neural network (DNN) computations in the mixed-signal domain with high energy efficiency but suffer from the tradeoff and limitations in their accuracy arising from analog nonidealities. Recently, circuit techniques were developed to support multi-bit analog computations in SRAM-based CIM macro [1], [2], which computes multiplication and accumulation by using transistor currents. However, the transistor current has nonlinear characteristics with respect to the gate voltage, significantly degrading the accuracies of DNNs. Some works address this problem by using charge-based computation [3], [4], where the multiplication results between 1b weight and multi-bit inputs are firstly stored in capacitors. Multi-bit-weight computations are then achieved by shifting and adding the multiplication result outputs either in the digital domain [3] or in the analog domain using a charge-sharing method [1]. The digital method typically requires a higher ADC precision and one ADC for every accumulation, becoming power heavy. The analog charge-sharing method requires switches to control, being exposed to charge injection noise and dissipating considerable power to turn on and off the switches. To address these issues, this work proposes an 8T1C SRAM-based CIM macro structure, which supports (1) multi-bit-weight charge-based computation without additional switches used for charge sharing; (2) a simple and fast computation where multi-bit-weight multiply-accumulate-averaging (MAV) voltage is immediately formed when the input is given, namely “one-step” computation; (3) compact 8T1C bit cell using metal-oxide-metal (MOM) capacitor which incurs only 1.5× cell area of the conventional 6T SRAM under logic rules; and (4) no additional power consumption in bit-shift for energy-efficient computing. We fabricated the proposed 4kb SRAM CIM macro in a 65nm process, whose structure is shown in Fig. 1, supporting a fully parallel computation of 1024 MAV operations with 64 4b inputs and 16 4b weights.
{"title":"A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation","authors":"E. Choi, Injun Choi, Chanhee Jeon, Gichan Yun, Donghyeon Yi, S. Ha, I. Chang, M. Je","doi":"10.1109/CICC53496.2022.9772821","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772821","url":null,"abstract":"Over the years, SRAM-based compute-in-memory (CIM) structures have shown ways to perform deep neural network (DNN) computations in the mixed-signal domain with high energy efficiency but suffer from the tradeoff and limitations in their accuracy arising from analog nonidealities. Recently, circuit techniques were developed to support multi-bit analog computations in SRAM-based CIM macro [1], [2], which computes multiplication and accumulation by using transistor currents. However, the transistor current has nonlinear characteristics with respect to the gate voltage, significantly degrading the accuracies of DNNs. Some works address this problem by using charge-based computation [3], [4], where the multiplication results between 1b weight and multi-bit inputs are firstly stored in capacitors. Multi-bit-weight computations are then achieved by shifting and adding the multiplication result outputs either in the digital domain [3] or in the analog domain using a charge-sharing method [1]. The digital method typically requires a higher ADC precision and one ADC for every accumulation, becoming power heavy. The analog charge-sharing method requires switches to control, being exposed to charge injection noise and dissipating considerable power to turn on and off the switches. To address these issues, this work proposes an 8T1C SRAM-based CIM macro structure, which supports (1) multi-bit-weight charge-based computation without additional switches used for charge sharing; (2) a simple and fast computation where multi-bit-weight multiply-accumulate-averaging (MAV) voltage is immediately formed when the input is given, namely “one-step” computation; (3) compact 8T1C bit cell using metal-oxide-metal (MOM) capacitor which incurs only 1.5× cell area of the conventional 6T SRAM under logic rules; and (4) no additional power consumption in bit-shift for energy-efficient computing. We fabricated the proposed 4kb SRAM CIM macro in a 65nm process, whose structure is shown in Fig. 1, supporting a fully parallel computation of 1024 MAV operations with 64 4b inputs and 16 4b weights.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128244481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772734
Zhaoqing Wang, S. Kim, K. Bowman, Mingoo Seok
This paper presents a review of the recent digital low-dropout voltage regulators (DLDOs). We have reviewed them in five aspects: control laws, triggering methods, power-FET circuit design, digital-analog hybridization, and single vs. distributed architectures. We then have surveyed and benchmarked more than 50 DLDOs published in the last decade. In addition, we have offered a new figure-of-merit (FoM) to address the shortcomings of the previously proposed FoMs. The benchmark provides insights on which techniques contribute to better dynamic load regulation performance. The survey and benchmark results are uploaded to a public repository.
{"title":"Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators","authors":"Zhaoqing Wang, S. Kim, K. Bowman, Mingoo Seok","doi":"10.1109/CICC53496.2022.9772734","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772734","url":null,"abstract":"This paper presents a review of the recent digital low-dropout voltage regulators (DLDOs). We have reviewed them in five aspects: control laws, triggering methods, power-FET circuit design, digital-analog hybridization, and single vs. distributed architectures. We then have surveyed and benchmarked more than 50 DLDOs published in the last decade. In addition, we have offered a new figure-of-merit (FoM) to address the shortcomings of the previously proposed FoMs. The benchmark provides insights on which techniques contribute to better dynamic load regulation performance. The survey and benchmark results are uploaded to a public repository.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123493411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772814
Joohwa Kim, Junyoung Park, J. Byun, Changkyu Seol, Chang-Soo Yoon, E. Shin, Hyunyoon Cho, Youngdo Um, Sucheol Lee, Hyungmin Jin, Kwangseob Shin, Hyunsub Norbert Rie, M. Jung, Jin-Hee Park, Gou Cha, Minjae Lee, Youngmin Kim, Byeori Han, Yuseong Jeon, Ji-Sang Lee, Hyejeong So, Sungduk Kim, Wansoo Park, Tae Young Kim, Youngdon Choi, J. Choi, Hyungjong Ko, Sang-Hyun Lee
The DRAM interface development to achieve a higher bandwidth has been requested according to the advance in massive computing technologies. Multi-level signaling, PAM-4 for example, is one of the most promising ways to address the requirement to extend the per-pin data rate without increasing clock frequency [1]. This paper suggests a single-ended PAM-4 transmitter for DRAM interface which requires high-speed operation. A 4-to-1 MUX based 2-tap feedforward equalizer (FFE) for bandwidth extension is used to mitigate the channel loss and inter-symbol interference (ISI). The impedance of each PAM-4 signal level can be controlled separately by applying thermometer switching in the main driver to achieve precise matching. The output driver of PAM-4 transmitter is optimized to have high linearity for operation of both low-voltage swing terminated logic (LVSTL) and pseudo open drain (POD). Also, a new timing skew training scheme for each PAM-4 signal level is developed to adjust timing for reducing clock skew in the internal path caused by PVT variations and bit error ratio (BER) increased by the non-linear characteristics of receiver. In addition, low power maximum transition avoidance (LPMTA) encoding is applied to decrease energy consumption of output driver. The prototype chip is fabricated in a 28nm CMOS process with adjusted channel length, not applying a minimum channel length, to mimic 10nm class DRAM process conditions. It is confirmed that propagation delay time (TPD) and $mathrm{I}_{text{dsat}}$ of prototype chip are well correlated with the parameters obtained by 10nm class DRAM process. Finally, 1.67-pJ/b of energy efficiency with 1.2V supply is measured at 60-Gb/s/pin with optimized single-ended PAM-4 transmitter.
{"title":"A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process","authors":"Joohwa Kim, Junyoung Park, J. Byun, Changkyu Seol, Chang-Soo Yoon, E. Shin, Hyunyoon Cho, Youngdo Um, Sucheol Lee, Hyungmin Jin, Kwangseob Shin, Hyunsub Norbert Rie, M. Jung, Jin-Hee Park, Gou Cha, Minjae Lee, Youngmin Kim, Byeori Han, Yuseong Jeon, Ji-Sang Lee, Hyejeong So, Sungduk Kim, Wansoo Park, Tae Young Kim, Youngdon Choi, J. Choi, Hyungjong Ko, Sang-Hyun Lee","doi":"10.1109/CICC53496.2022.9772814","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772814","url":null,"abstract":"The DRAM interface development to achieve a higher bandwidth has been requested according to the advance in massive computing technologies. Multi-level signaling, PAM-4 for example, is one of the most promising ways to address the requirement to extend the per-pin data rate without increasing clock frequency [1]. This paper suggests a single-ended PAM-4 transmitter for DRAM interface which requires high-speed operation. A 4-to-1 MUX based 2-tap feedforward equalizer (FFE) for bandwidth extension is used to mitigate the channel loss and inter-symbol interference (ISI). The impedance of each PAM-4 signal level can be controlled separately by applying thermometer switching in the main driver to achieve precise matching. The output driver of PAM-4 transmitter is optimized to have high linearity for operation of both low-voltage swing terminated logic (LVSTL) and pseudo open drain (POD). Also, a new timing skew training scheme for each PAM-4 signal level is developed to adjust timing for reducing clock skew in the internal path caused by PVT variations and bit error ratio (BER) increased by the non-linear characteristics of receiver. In addition, low power maximum transition avoidance (LPMTA) encoding is applied to decrease energy consumption of output driver. The prototype chip is fabricated in a 28nm CMOS process with adjusted channel length, not applying a minimum channel length, to mimic 10nm class DRAM process conditions. It is confirmed that propagation delay time (TPD) and $mathrm{I}_{text{dsat}}$ of prototype chip are well correlated with the parameters obtained by 10nm class DRAM process. Finally, 1.67-pJ/b of energy efficiency with 1.2V supply is measured at 60-Gb/s/pin with optimized single-ended PAM-4 transmitter.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121460392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772824
Zixiao Lin, Yan Lu, Fangyu Mao, Chuang Wang, R. Martins
High power density wireless fast charging is an attractive feature for mobile devices. In this paper, we propose a wireless power receiver (RX) with rectification through a split-dual-path and a step-down conversion obtained with a merged switched-capacitor-inductor hybrid-quad-path (S2H4). In such architecture, in the LC tank (rivers' source) the currents separate into multiple paths (rivers) and finally all flow into the battery (the sea).
{"title":"All Rivers Flow to the Sea: A High Power Density Wireless Power Receiver with Split-Dual-Path Rectification and Hybrid-Quad-Path Step-Down Conversion","authors":"Zixiao Lin, Yan Lu, Fangyu Mao, Chuang Wang, R. Martins","doi":"10.1109/CICC53496.2022.9772824","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772824","url":null,"abstract":"High power density wireless fast charging is an attractive feature for mobile devices. In this paper, we propose a wireless power receiver (RX) with rectification through a split-dual-path and a step-down conversion obtained with a merged switched-capacitor-inductor hybrid-quad-path (S2H4). In such architecture, in the LC tank (rivers' source) the currents separate into multiple paths (rivers) and finally all flow into the battery (the sea).","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"16 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772846
S. Sonkusale
Conventional medicine relies on a one-size-fits-all standard of care which does not account for diffences in the complexity of disease between individuals and their responses to treatment. New and more effective approach for healthcare demands personalized approach to treatment. This requires measuring the relevant markers of health and disease including but not limited to the metabolic state of an individual, but also the overall diet/nutrition profile, physical activity, lifestyle, and the environmental parameters. Measurement is performed by a suite of sensors, both physical and chemical and their electronic interfaces, whereas treatments are prescribed in the form of drugs or change in diet/nutrition or exercise, with the goal of improving the health of an individual in the shortest time. From a circuits and systems perspective, this resembles a closed loop feedback system with human as a complex dynamical system monitored by a suite of physical chemical and biological sensors and actuated via several treatments/therapies with precise timing, quantity and intesity. For such feedback system built with human-in-the-Ioop, the following requirements should be met: (1) Device should have an intimate reliable interface with human body and tissue (2) It should be bio-compatible (3) It should be minimally invasive and possibly inconspicous to the individual and (4) It should operate continuously or in real-time, commensurate with the underlying dynamics of the biomarker being monitored, and/or the timeliness and frequency at which treatment is being delivered. Flexible bioelectronics[2], [3] is an emerging area of research and development where devices for sensing, actuation, microfluidics, therapy, computing and communication are engineered for bio-integration to address the aforementioned fundamental challenges.
{"title":"Smart Threads for Tissue-Embedded Bioelectronics","authors":"S. Sonkusale","doi":"10.1109/CICC53496.2022.9772846","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772846","url":null,"abstract":"Conventional medicine relies on a one-size-fits-all standard of care which does not account for diffences in the complexity of disease between individuals and their responses to treatment. New and more effective approach for healthcare demands personalized approach to treatment. This requires measuring the relevant markers of health and disease including but not limited to the metabolic state of an individual, but also the overall diet/nutrition profile, physical activity, lifestyle, and the environmental parameters. Measurement is performed by a suite of sensors, both physical and chemical and their electronic interfaces, whereas treatments are prescribed in the form of drugs or change in diet/nutrition or exercise, with the goal of improving the health of an individual in the shortest time. From a circuits and systems perspective, this resembles a closed loop feedback system with human as a complex dynamical system monitored by a suite of physical chemical and biological sensors and actuated via several treatments/therapies with precise timing, quantity and intesity. For such feedback system built with human-in-the-Ioop, the following requirements should be met: (1) Device should have an intimate reliable interface with human body and tissue (2) It should be bio-compatible (3) It should be minimally invasive and possibly inconspicous to the individual and (4) It should operate continuously or in real-time, commensurate with the underlying dynamics of the biomarker being monitored, and/or the timeliness and frequency at which treatment is being delivered. Flexible bioelectronics[2], [3] is an emerging area of research and development where devices for sensing, actuation, microfluidics, therapy, computing and communication are engineered for bio-integration to address the aforementioned fundamental challenges.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114689155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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